Mosys | More Than Memory
Time 2022-10-17 18:42:37Web Name: Mosys | More Than Memory
WebSite: http://www.mosys.com
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Customer PortalLoginRegister PERASO INC…A POWERFUL 5G COMPANY CREATED BY MERGING TWO INDUSTRY LEADERS, PERASO TECHNOLOGIES AND MOSYS QUAZAR QPR Memory for FPGAs
A single Quazar QPR memory IC replaces 4 to 8 QDR devices and expands the onboard FPGA memory with high speed, high-capacity SRAM. Board complexity, design, debug, and costs are all reduced by using only 4 to 16 serial SERDES connections.
FEATURES: High Capacity, low latency - 576Mb or 1Gb• Single device replaces 4 to 8 QDRs Better performance/lower cost than QDR Bandwidth up to 640 Gbps, Low tRC Supports Dual Port Memory TYPICAL APPLICATIONS: Replace QDR, RLDRAM or free up HBM Oversubscription Buffers Table Lookup bE LineCards and Switches BLAZAR BANDWIDTH ACCELERATOR ENGINES for FPGAs
BLAZAR BANDWIDTH ACCELERATOR ENGINES for FPGAs
A single Blazar Bandwidth Accelerator Engine IC provides In-Memory Compute that accelerates functions and adds high capacity, low latency memory for high bandwidth, low latency applications.
FEATURES: In-memory compute 640 Gbps, 5 Billion reads per second Optional 32 RISC cores for higher compute Supports Dual Port Memory 576Mb or 1Gb memory included TYPICAL APPLICATIONS: SmartNIC & SmartSwitch Metering and Statistics – trTCAM 5G UPF and BNG offload Serial Link Aggregation STELLAR Packet Classification IP for FPGAs
STELLAR Packet Classification IP for FPGAs
Stellar Packet Classification Platform IP supports ultra-high search performance using lookup rules based on highly complex Access Control List (ACL) and Longest Prefix Match (LPM).
FEATURES: 100s of millions of lookups per second 25Gbps to 1Tbps+ Millions of complex rules Up to 480b keys Live Updates TYPICAL APPLICATIONS: 5G UPF and BNG IPV4/6 address lookup and routing Network Firewall & Anti-DDos High–Reliability Systems LineSpeed
LineSpeed
The LineSpeed FLEX family is a set of 100G PHY products supporting a variety of retimer, gearbox, multiplexing, and redundant link functions. These are typically used on line cards or inside modules and support multiple data rates and 10G, 25G, and 100G industry standards.
FEATURES: On-chip 100G RS-FEC for Gearbox and Retimer Multi-Link Gearbox (MLG) for dense 10GbE aggregation Retimer is protocol independent with mixed port speeds Serial Mux/Demux to increase system throughput Common register structure and package footprints TYPICAL APPLICATIONS: 100GbE LineCards and Switches 10GbE Port Aggregation Serial Link Aggregation High-Reliability Systems
A single Quazar QPR memory IC replaces 4 to 8 QDR devices and expands the onboard FPGA memory with high speed, high-capacity SRAM. Board complexity, design, debug, and costs are all reduced by using only 4 to 16 serial SERDES connections.
A single Blazar Bandwidth Accelerator Engine IC provides In-Memory Compute that accelerates functions and adds high capacity, low latency memory for high bandwidth, low latency applications.
Stellar Packet Classification Platform IP supports ultra-high search performance using lookup rules based on highly complex Access Control List (ACL) and Longest Prefix Match (LPM).
The LineSpeed FLEX family is a set of 100G PHY products supporting a variety of retimer, gearbox, multiplexing, and redundant link functions. These are typically used on line cards or inside modules and support multiple data rates and 10G, 25G, and 100G industry standards.
FEATURES: High Capacity, low latency - 576Mb or 1Gb• Single device replaces 4 to 8 QDRs Better performance/lower cost than QDR Bandwidth up to 640 Gbps, Low tRC Supports Dual Port Memory TYPICAL APPLICATIONS: Replace QDR, RLDRAM or free up HBM Oversubscription Buffers Table Lookup bE LineCards and Switches FEATURES: In-memory compute 640 Gbps, 5 Billion reads per second Optional 32 RISC cores for higher compute Supports Dual Port Memory 576Mb or 1Gb memory included TYPICAL APPLICATIONS: SmartNIC & SmartSwitch Metering and Statistics – trTCAM 5G UPF and BNG offload Serial Link Aggregation FEATURES: 100s of millions of lookups per second 25Gbps to 1Tbps+ Millions of complex rules Up to 480b keys Live Updates TYPICAL APPLICATIONS: 5G UPF and BNG IPV4/6 address lookup and routing Network Firewall & Anti-DDos High–Reliability Systems FEATURES: On-chip 100G RS-FEC for Gearbox and Retimer Multi-Link Gearbox (MLG) for dense 10GbE aggregation Retimer is protocol independent with mixed port speeds Serial Mux/Demux to increase system throughput Common register structure and package footprints TYPICAL APPLICATIONS: 100GbE LineCards and Switches 10GbE Port Aggregation Serial Link Aggregation High-Reliability Systems Press Releases
MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units
Dec 9, 2021 MoSys Stockholders Approve Business Combination with Peraso Technologies
Dec 2, 2021 MoSys Announces Preliminary Stockholder Voting Results Approving the Arrangement with Peraso, Provides Transaction Update
Dec 1, 2021 MoSys Announces Adjournment of Special Meeting to December 1, 2021; Urges Eligible Stockholders to Vote
Nov 23, 2021 MoSys, Inc. Urges Stockholders to Vote for Proposed Business Combination with Peraso Technologies, Leading 5G mmWave Company
Nov 17, 2021 Use Cases
Virtual Accelerator EnginesPacket Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL LookupsPacket Classification for Next Generation Network FirewallsPacket Classification in Cloud and Enterprise Datacenters Keeping Up with 4X the LPM Routing DemandPacket Classification in 5G UPF (User Plane Function) Fixing LPM Routing Bottlenecks in New 5G NetworksAccelerator EnginesExpanding High-Speed FPGA MemoryMoSys Bandwidth Engine ICs for Test & Measurement ApplicationsFPGA AccelerationFPGA Reference DesignsMetro EthernetEdge RouterData Center SecurityRoutersVideoData Center SDN SwitchLineSpeedDense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link GearboxRedundant Link Mode for High-Rel Data TransferMultiplexing and Demultiplexing High-Speed Serial LinksBringing 100Gb Ethernet RS-FEC to Low-Cost FPGAs Blog
Utilizing Synchronous Ethernet Timing in 10GbE Breakout from a 100G Multi-Link Gearbox (MLG)
October 5, 2021 Giving Your FPGA a Big Boost
September 28, 2021 Not All Memory Chips Are Created Equal
September 2, 2021 Dense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link Gearbox
August 18, 2021 The Benefits of a Dual Port in Data Acquisition
August 9, 2021 Are You Ready For HyperSpeed
FEATURES: In-memory compute 640 Gbps, 5 Billion reads per second Optional 32 RISC cores for higher compute Supports Dual Port Memory 576Mb or 1Gb memory included TYPICAL APPLICATIONS: SmartNIC & SmartSwitch Metering and Statistics – trTCAM 5G UPF and BNG offload Serial Link Aggregation FEATURES: 100s of millions of lookups per second 25Gbps to 1Tbps+ Millions of complex rules Up to 480b keys Live Updates TYPICAL APPLICATIONS: 5G UPF and BNG IPV4/6 address lookup and routing Network Firewall & Anti-DDos High–Reliability Systems FEATURES: On-chip 100G RS-FEC for Gearbox and Retimer Multi-Link Gearbox (MLG) for dense 10GbE aggregation Retimer is protocol independent with mixed port speeds Serial Mux/Demux to increase system throughput Common register structure and package footprints TYPICAL APPLICATIONS: 100GbE LineCards and Switches 10GbE Port Aggregation Serial Link Aggregation High-Reliability Systems Press Releases
MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units
Dec 9, 2021 MoSys Stockholders Approve Business Combination with Peraso Technologies
Dec 2, 2021 MoSys Announces Preliminary Stockholder Voting Results Approving the Arrangement with Peraso, Provides Transaction Update
Dec 1, 2021 MoSys Announces Adjournment of Special Meeting to December 1, 2021; Urges Eligible Stockholders to Vote
Nov 23, 2021 MoSys, Inc. Urges Stockholders to Vote for Proposed Business Combination with Peraso Technologies, Leading 5G mmWave Company
Nov 17, 2021 Use Cases
Virtual Accelerator EnginesPacket Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL LookupsPacket Classification for Next Generation Network FirewallsPacket Classification in Cloud and Enterprise Datacenters Keeping Up with 4X the LPM Routing DemandPacket Classification in 5G UPF (User Plane Function) Fixing LPM Routing Bottlenecks in New 5G NetworksAccelerator EnginesExpanding High-Speed FPGA MemoryMoSys Bandwidth Engine ICs for Test & Measurement ApplicationsFPGA AccelerationFPGA Reference DesignsMetro EthernetEdge RouterData Center SecurityRoutersVideoData Center SDN SwitchLineSpeedDense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link GearboxRedundant Link Mode for High-Rel Data TransferMultiplexing and Demultiplexing High-Speed Serial LinksBringing 100Gb Ethernet RS-FEC to Low-Cost FPGAs Blog
Utilizing Synchronous Ethernet Timing in 10GbE Breakout from a 100G Multi-Link Gearbox (MLG)
October 5, 2021 Giving Your FPGA a Big Boost
September 28, 2021 Not All Memory Chips Are Created Equal
September 2, 2021 Dense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link Gearbox
August 18, 2021 The Benefits of a Dual Port in Data Acquisition
August 9, 2021 Are You Ready For HyperSpeed
FEATURES: 100s of millions of lookups per second 25Gbps to 1Tbps+ Millions of complex rules Up to 480b keys Live Updates TYPICAL APPLICATIONS: 5G UPF and BNG IPV4/6 address lookup and routing Network Firewall & Anti-DDos High–Reliability Systems FEATURES: On-chip 100G RS-FEC for Gearbox and Retimer Multi-Link Gearbox (MLG) for dense 10GbE aggregation Retimer is protocol independent with mixed port speeds Serial Mux/Demux to increase system throughput Common register structure and package footprints TYPICAL APPLICATIONS: 100GbE LineCards and Switches 10GbE Port Aggregation Serial Link Aggregation High-Reliability Systems Press Releases
MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units
Dec 9, 2021 MoSys Stockholders Approve Business Combination with Peraso Technologies
Dec 2, 2021 MoSys Announces Preliminary Stockholder Voting Results Approving the Arrangement with Peraso, Provides Transaction Update
Dec 1, 2021 MoSys Announces Adjournment of Special Meeting to December 1, 2021; Urges Eligible Stockholders to Vote
Nov 23, 2021 MoSys, Inc. Urges Stockholders to Vote for Proposed Business Combination with Peraso Technologies, Leading 5G mmWave Company
Nov 17, 2021 Use Cases
Virtual Accelerator EnginesPacket Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL LookupsPacket Classification for Next Generation Network FirewallsPacket Classification in Cloud and Enterprise Datacenters Keeping Up with 4X the LPM Routing DemandPacket Classification in 5G UPF (User Plane Function) Fixing LPM Routing Bottlenecks in New 5G NetworksAccelerator EnginesExpanding High-Speed FPGA MemoryMoSys Bandwidth Engine ICs for Test & Measurement ApplicationsFPGA AccelerationFPGA Reference DesignsMetro EthernetEdge RouterData Center SecurityRoutersVideoData Center SDN SwitchLineSpeedDense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link GearboxRedundant Link Mode for High-Rel Data TransferMultiplexing and Demultiplexing High-Speed Serial LinksBringing 100Gb Ethernet RS-FEC to Low-Cost FPGAs Blog
Utilizing Synchronous Ethernet Timing in 10GbE Breakout from a 100G Multi-Link Gearbox (MLG)
October 5, 2021 Giving Your FPGA a Big Boost
September 28, 2021 Not All Memory Chips Are Created Equal
September 2, 2021 Dense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link Gearbox
August 18, 2021 The Benefits of a Dual Port in Data Acquisition
August 9, 2021 Are You Ready For HyperSpeed
FEATURES: On-chip 100G RS-FEC for Gearbox and Retimer Multi-Link Gearbox (MLG) for dense 10GbE aggregation Retimer is protocol independent with mixed port speeds Serial Mux/Demux to increase system throughput Common register structure and package footprints TYPICAL APPLICATIONS: 100GbE LineCards and Switches 10GbE Port Aggregation Serial Link Aggregation High-Reliability Systems Press Releases
MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units
Dec 9, 2021 MoSys Stockholders Approve Business Combination with Peraso Technologies
Dec 2, 2021 MoSys Announces Preliminary Stockholder Voting Results Approving the Arrangement with Peraso, Provides Transaction Update
Dec 1, 2021 MoSys Announces Adjournment of Special Meeting to December 1, 2021; Urges Eligible Stockholders to Vote
Nov 23, 2021 MoSys, Inc. Urges Stockholders to Vote for Proposed Business Combination with Peraso Technologies, Leading 5G mmWave Company
Nov 17, 2021 Use Cases
Virtual Accelerator EnginesPacket Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL LookupsPacket Classification for Next Generation Network FirewallsPacket Classification in Cloud and Enterprise Datacenters Keeping Up with 4X the LPM Routing DemandPacket Classification in 5G UPF (User Plane Function) Fixing LPM Routing Bottlenecks in New 5G NetworksAccelerator EnginesExpanding High-Speed FPGA MemoryMoSys Bandwidth Engine ICs for Test & Measurement ApplicationsFPGA AccelerationFPGA Reference DesignsMetro EthernetEdge RouterData Center SecurityRoutersVideoData Center SDN SwitchLineSpeedDense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link GearboxRedundant Link Mode for High-Rel Data TransferMultiplexing and Demultiplexing High-Speed Serial LinksBringing 100Gb Ethernet RS-FEC to Low-Cost FPGAs Blog
Utilizing Synchronous Ethernet Timing in 10GbE Breakout from a 100G Multi-Link Gearbox (MLG)
October 5, 2021 Giving Your FPGA a Big Boost
September 28, 2021 Not All Memory Chips Are Created Equal
September 2, 2021 Dense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link Gearbox
August 18, 2021 The Benefits of a Dual Port in Data Acquisition
August 9, 2021 Are You Ready For HyperSpeed
Press Releases
MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units
Dec 9, 2021MoSys Stockholders Approve Business Combination with Peraso Technologies
Dec 2, 2021MoSys Announces Preliminary Stockholder Voting Results Approving the Arrangement with Peraso, Provides Transaction Update
Dec 1, 2021MoSys Announces Adjournment of Special Meeting to December 1, 2021; Urges Eligible Stockholders to Vote
Nov 23, 2021MoSys, Inc. Urges Stockholders to Vote for Proposed Business Combination with Peraso Technologies, Leading 5G mmWave Company
Nov 17, 2021Use Cases
Virtual Accelerator EnginesPacket Classification for Anti-Distributed Denial of Service (DDoS) Engines – Combining AI/ML with ACL LookupsPacket Classification for Next Generation Network FirewallsPacket Classification in Cloud and Enterprise Datacenters Keeping Up with 4X the LPM Routing DemandPacket Classification in 5G UPF (User Plane Function) Fixing LPM Routing Bottlenecks in New 5G NetworksAccelerator EnginesExpanding High-Speed FPGA MemoryMoSys Bandwidth Engine ICs for Test & Measurement ApplicationsFPGA AccelerationFPGA Reference DesignsMetro EthernetEdge RouterData Center SecurityRoutersVideoData Center SDN SwitchLineSpeedDense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link GearboxRedundant Link Mode for High-Rel Data TransferMultiplexing and Demultiplexing High-Speed Serial LinksBringing 100Gb Ethernet RS-FEC to Low-Cost FPGAsBlog
Utilizing Synchronous Ethernet Timing in 10GbE Breakout from a 100G Multi-Link Gearbox (MLG)
October 5, 2021Giving Your FPGA a Big Boost
September 28, 2021Not All Memory Chips Are Created Equal
September 2, 2021Dense 10GbE Breakout from a 100G (4x25G) Port Using Multi-Link Gearbox
August 18, 2021The Benefits of a Dual Port in Data Acquisition
August 9, 2021Are You Ready For HyperSpeed
MoSys’ products focus on Accelerating applications to what we call HyperSpeed. This requires identifying every area in a system that affects speed and finding solutions to increase performance. Some applications may use all of our products in a single system. In those cases, we facilitate increasing performance to get closer to achieving HyperSpeed!
Quazar Family
Quazar Quad Partition Rate MemoriesBlazar Family
PHE-Programmable HyperSpeed Engine Memory IC Blazar Family Overview BE3RMW - Bandwidth Engine 3 - RMW BE3BURST-Bandwidth Engine 3 - BURST BE2RMW-Bandwidth Engine 2-RMW BE2BURST - Bandwidth Engine 2 - BURSTStellar Family
LineSpeed Family
LineSpeed Family Overview 100G Octal Retimer with RS-FEC 100G Full-Duplex Retimer with RS-FEC 10 Lane Full Duplex 25G Retimer with FEC 100G Gearbox with RS-FEC 100G Multi-Link Gearbox (MLG) for Modules 100G Multi-Link Gearbox (MLG) for Line Cards Multi-Channel 2:1 Serial Mux/DemuxLets stay connected.
MoSys’ innovative Memory ICs improve system speed and performance while eliminating data throughput and access bottlenecks on line cards and systems with aggregate rates above 100Gbps.
ProductsQuazar FamilyBlazar FamilyLine Speed FamilyDevelopment KitsApplicationsDesign SupportInvestor RelationCorporate GovernanceInvestor InformationInvestment FAQSEC FilingsIRS FormsPress ReleasesContact UsContact SalesContact App SupportRegister for UpdatesRegister for PortalSales Offices© 2022 MoSys, Inc.
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