Robust Low Power VLSI

Web Name: Robust Low Power VLSI






A COTS Based Low Power Wireless ECG Sensor In this project, a low power wireless ECG sensor is implemented using commercial off the shelf (COTS) components. The resulting system can acquire and process ECG data and send it wirelessly to a basestation such as a handheld device. The picture shows the ECG sensor in operation, with the PDA plotting the real time ECG signal. Sub-Threshold FPGAs This work explores reconfigurable circuits operating at low voltages. While the existing FPGAs are too high power to meet the requirements of IoT applications, we designed and optimized new circuit typologies of CLBs and global interconnect in near/sun-threshold region. We also developed custom tool flow to support full chip configuration. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-threshold FPGA using conventional circuits and 22X less energy than an equivalent FPGA at full VDD. We are currently working towards dynamic voltage scaling and measurements using real-life applications. Artificial Seal Whisker Animal research activities conducted under NMFS permit 14535The artificial seal whisker project is a joint effort with the University of Virginia’s Mechanical Engineering Department and the University of California Santa Cruz to detect and track underwater wakes using an array of bio-inspired sensors. Previous biological work found harbor seals are able to track wakes using only their whiskers. In this project, the seal whisker team is focused on understanding how seals sense wakes using their whiskers, designing a capacitance based whisker-like sensor, and designing the electrical backend printed circuit board for sensing, storing, and transmitting data. The biologically inspired sensor’s design is based on seal whiskers and previous effort in the field involving spider hairs and fish lateral lines. All components will be integrated in the Wake Information Detection and Tracking System (WIDTS) to be carried by a trained harbor seal for testing. Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS This paper investigates the effect of body biasing on the leakage and delay of dynamic leakage suppression (DLS) logic. We present a brief theoretical analysis of the impact of body biasing on DLS logic as well as measurements from a test chip in 65nm CMOS. Results show that forward body biasing can reduce delay by up to 41X with negligible impacts on leakage. A 0.6V 44.6fJ/cycle Energy-Optimized Frequency-Locked Loop in 65nm CMOS with 20.3ppm/°C Stability This letter presents an energy efficient, temperature-compensated frequency-locked loop (FLL) for use as an on-chip clock source. We first present a fully integrated FLL architecture that significantly improves energy efficiency by using a loop divider to boost the output frequency without requiring increased static power dissipation. We develop models for the FLL energy-per-cycle and temperature stability and use them to implement an energy-optimized and highly temperature-stable FLL design in 65-nm CMOS that achieves 20.3-ppm/◦C temperature stability from −20 ◦C to 60 ◦C and an energy efficiency of 44.6-fJ/cycle at 23 ◦C (45.3 nW at 1.016 MHz), which is the highest energy efficiency reported to date for a fully on-chip oscillator, regardless of architecture, operating frequency, or temperature stability.

TAGS:Low Robust VLSI 

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