Electronics and Integrated Circuits Design, Engineering and Semiconductor Expert Services

Web Name: Electronics and Integrated Circuits Design, Engineering and Semiconductor Expert Services

WebSite: http://www.advlsi.com





ADVLSI                  Analog DigitalVery Large Scale Integrated CircuitsUSA-based Experience and Capabilities*    Full-custom IC, ASIC, PCB, FPGA, MCU, MPU and Memory designs.*    Wide range of applications, including high-performance RF, Analogand Digital electronics,optimization for high-speed or low-power.*    Design and manufacturing costs reduction.*    Design for Testability and Manufacturability.*    Detailed documentation for Quality Assurance and ContractManufacturing.Since1986, diligently served and designed for more than 40 companies, mostly inSilicon Valley.Track record of successful analog and mixed-signalIC designs: RF wireless transceivers, multi-Gbpswireline I/O (HSTL, LVCMOS, LVDS,PECL, BTL), HV I/O Buffers, SerDes, ADC, Video DAC,PLL,DC voltage converters, power management anddistribution, analog micropower IC, SRAM's, EPROM,Microprocessors (MPU), FPGA prototypes and embeddedMicrocontroller (MCU) applications, 2.5/3DIC packages (CSP and MCM), fine-line PCB, signalintegrity, EMI- RFI and ESD protection.Team building of experts in VLSI, MEMS, 2.5/3D IC packaging, Mechatronics,RF antennas,microwave hardware, wireless communication protocols (WiFi, LTE, 5G), embeddedprocessors, software development for real-time applications, Data Analytics and ArtificialIntelligence.We are well prepared to solve new product development challenges for:the Internet-of-Things, Wireless Sensor Networks and Remote Control with micro-actuators.CADtools:     Tanner EDA VLSI Pro(L-Edit, T-SPICE), HiPer Silicon, Alliance VLSITools,Icarus Verilog, Verilog-A, Altera Quartus II, Aldec HDL Express,Altium Designer, NI LabVIEW,NI Electronics Workbench, Mathcad,IAR Embedded Workbench, Comsol Multiphysics, Sonnet,SolidWorks.Programming languages:     C, UNIX Shell, Sed, Perl, AWK, Verilog, Verilog-A.Project management tools:   MS Project, MS Office Suite.Portfolioof consulting service, product and IP development projectsRFID Tags, ADC: pipelined, flash and SD, DAC, PLL, DC power converters, charge pumps and V/Iregulators, RF transceivers, SRAM,CAM, non-volatile memories, Network processors.Consulting on I/O buffers and pad rings (PECL, LVDS,HSTL, LVCMOS, PCI, BTL), ESD and latch-upprotection circuits, backplane and PCBsignal integrity analysis, IC and PofL powerdistribution, noiseimmunity, BGA and flip-chippackaging, frequency synthesis, clock distribution networks, circuit timingand testability, IofT-enabling hardware and software tools.List of projects from 2000 to presentMost recent:*    Consulting, IC design and technology development in CMOS 30/20 nmtechnology for Digital, andAnalog Mixed-Signals applications, integrating a new type of Si devices toproduce better integrationdensity than a FinFET-based 16 nm CMOS technology.*    Design of VLSI Digital, SRAM, CAM and Analog circuit cells toshow the feasibility.*    VLSI CAE/D method and development plans. Devicephysics and models.*    VLSI fabrication plan with CMOS Si IC foundry,including new Si die processing steps, photomaskand circuit design rules.*    Product and IP development plan for Internet-of-Things, RF radioand communication processorfor 5G, sensor interface circuits, communication network processor based onopen source computinglibrary, and cybersecurity hardware engine.*    International patent application filed, with most claimsapproved: WO2016057973-A1.Other work and projects, with most designs releasedto production:[56]      Consultingon encapsulated power supplies and drivers of LED lamps, circuit simulation            of electrothermal effects. Systemarchitecture, design partitioning: HW-SW, PCB and IC             partition, MCU anddevelopment tools. Definition of DFTM flow and test benches.            Solutions and impact of 3-D integration and packaging.[55]      Consultingon the micro-architecture, circuit design and development plan ofphotonic-based            transceivers for Hybrid Memory Cube.[54]      Consultingon the technologies and markets for Passive Optical Network components: FTTH/X            deployment, integration of fiber-optic connectivity intoPC’s and Si dice.[53]      Consultingon wireless electrical power converter and transceiver for medical implant.[52]      CMOSRF Transceiver 5GHz, concept design in 0.13 mm CMOS MiM-L C.[51]      SynchronousSRAM in 0.13mm CMOS, circuit design, IC mask layout,memory block assembler            proven by two blocks (128X12 to 8192X64 bits) embedded inproduct released to production;            SRAM assembler/compiler program written in Perl script and L-EditUPI macro.[50]      Design of a micropowerRF transponder for a battery-operated RFID Tag in 0.50 mm CMOS             process and withMOSFET’s operating in weak inversion.[49]      Design of a bipolar OpAmpfor EMI application ( VCC 6 V to 30 V, ICC 15 mA, cap. Load            up to 20 nF, DC gain 80 dB, UGB 80 MHz, SR 350 V/µs with CL50 pF, DC output swing 80 %            of VCC) with power down control.[48]      Redesign and IC mask layout of 5V-tolerantI/O Buffers and ESD protection circuit of            aCrystal/RC Oscillator Pad, in a CMOS 0.35 mm technology.[47]      Designin SOI CMOS 0.13mm technology of programmable voltagegenerators for VLSI             applications and SRAMwith high dynamic load (500 mA peak and 500 pstransients),            combining coarse and fine voltage regulation loops. [46]      Designin SOI CMOS 0.13mm technology of HSTL and LVCMOS I/O withcalibration.[45]      Designin SOI CMOS 0.13mm technology of a high-current negativevoltage (-2.0V 2.0mA)            generator  with smartpower regulation: US Patent 6,756,838(invented the concept and technique,            most of the detailed design, guided the team to write thepatent).[44]      NovelESD Protection Circuit for dense VLSI dice in a SOI CMOS 0.13 mm technology:            USPatent 7,187,530 (invented the concept and technique, most of the detailed designguided            the team to write the patent).[43]      Design of a video analog front end in aCMOS 0.25 mm technology. Pipelined ADC’s with 8/10-bit            ENOB, 175/30 MSpssampling rate, digital error calibration, programmable input clamp, detection            ofsynchronization pulse and HSYNC/VSYNC separation, PLL and frequencysynthesizer.[42]      Architectureand first-pass design in a CMOS 0.18 mm technology of a SerDes CDR and LVDS            parallel bus interface (16-bit wide data and 1 clock) with adata transfer rate of 1.56 Gbytes/second.[41]      Design in a BiCMOS0.80 mmtechnology of a micropower undervoltage/end-of-chargedetector            for batterymonitoring in cellular phones and portable equipment (LMS33460). Pure Analog IC            design.First prototype qualified to full technical specifications, and photomask settransferred            tolarge-scale production at first ICML tapeout.[40]      Architectureand first-pass design of a 12bit ADC and data acquisition IC in a Silicon BiCMOS            technology (0.80 mm scalable to 0.50 mm with no redesign).  Samplingrate 1GSps, 11-bit ENOB,            dual port FIFO buffer, open/closed loop auto calibration andBIST modes.Listof projects prior to 2000[39]      IClayout floor-planning, power and clocks distribution networks, place-and-routeand post-layout            verification of 2D/3D graphics and video VLSI processors,using Avant! XO, Planet and Apollo            VLSI CAD tools.[38]      CMOS0.35mm I/O buffers and ESD protection circuits. Designfor reliability of I/O periphery            and power distribution of VLSI circuits. Packagingand signal integrity issues.[37]      Circuitdesign and IC mask layout of a DLL-based clock distribution IC: PLX EQ6610.[36]      TTL-BTLbus transceivers for Futurebus or similar backplanebus applications, designed in            the Philips Semiconductor BiCMOS0.80 mm (QuBiC) technology. [35]      BiCMOS cell library for RF communication: bandgap voltageand current reference generators,            LNA,mixer, PLL and sigma-delta modulator for fractional-N frequency synthesizer,phase            and frequency modulator, RF output amplifier.[34]      PECLI/O buffers for 3.30 V / 5.0 V operation, 4.0 mils padpitch, with excellent ESD protection            and latch-up immunity, programmable impedance matching andIC calibration.            Clockdistribution network and I/O periphery of Intel PCI-to-ISA and PCI-to-PCIbridges            for laptop PC and docking station.[33]      Conversionof a digital camera memory and CCD sensor controller from a XC4000 FPGA            to a Chip Express QYH500 gate array. Behavioral and RTLmodel in VHDL, logic synthesis,            test bench and test suites, fault grading and production testvectors.[32]      Managementof the VLSI design team implementing a LAN switch for NEC America.            Microarchitecture and test specifications, behavioral and RTLmodeling.[31]      DRAMController for a C-Cube MPEG1 video processor used in a karaoke CDROM player.            VerilogRTL modeling and translation of behavioral model written in C, Synopsys logic            synthesis into a CMOS standard cell library, test bench andtest suite.[30]      CMOScell library implementing the JTAG 1149.1 IEEE standard. Post-layout timinganalysis            of R3081, using Dracula LPE, Timemilland Hspice. Netlist parser and path extractionwritten            in C and Unix C-shell, sed and awk scripts.[29]      CMOScircuit design, low-power and high-speed tradeoffs, optimization of Logic andspecific            blocks for the compaction of the Intel Pentium for laptopPCs.[28]      Designof the Instruction Cache for the Intel Pentium (P5 Rev. 1).            Consulting on BiCMOS technology andcircuit design techniques.[27]      Circuitdesign and logic optimization of the Intel H4C/80486SL, 80486SX.[26]      Designof a PLL in CMOS 0.80mm technology, 100MHz clocksynthesizer, Logic synchronizer.            bandgap regulator, programmable loop filter and outputfrequencies, lock detection.[25]      Cachecontroller tag memory of the Intel 80386SL: first microprocessor integratingcache            and DRAM controllers, the full AT chipset. MPU released toproduction at first ICML-TO            and elected product of the year by Fortune Magazine.[24]      Hardwarebehavioral modeling and test benches using Verilog and C-PLI from the component            data sheets and functional specifications of the TMS44C251Video RAM, WD33C93 SCSI            Controller, Am7990 Ethernet LAN Controller.[23]      Circuitdesign and IC layout of a BiCMOS gate array masterand programmable I/O buffers            in Cypress Semiconductor BiCMOS0.80 mm technology.[22]      Designof a 4KX4 ECL SRAM in Cypress Semiconductor BiCMOS0.80 mm technology.[21]      BinaryCAM-based Translation Lookaside Buffer for Fujitsu SPARC chipset, in CMOS 1.0 mm            and 0.80 mm technologies.[20]      Designof the hardware and PCB for a X-Terminal, using the80386 CPU, 80387 Floating Point            coprocessor, cache memory controller, Am7990 Ethernet LANController, Chips Technologies            PC-AT chipset, National Semiconductor DP8500 Graphics Engine.[19]      Designof a Smart Card system: EEPROM-based data carrier, RF and IR transceivers, LCD,I/O            controller using the Motorola MC68HC05/11 MCU. Prototype PCB and firmware development.[18]      Designof a GDT Silicon Compiler library for embedded microcontroller applicationsusing            the 8051 instruction set.[17]      BiCMOS cell library and design flow, Dracula DRC, ERC, LVSand LPE rules and set-up files.[16]      Designof 256 Kbits and 64 Kbits SRAM in BiCMOS 1.0-mm technology (ECL/CML techniques).[15]      Designof a RAMDAC equivalent to the Brooktree Bt458, with125 MHz operating frequency,            in a CMOS 1.25-mm two-metal technology.[14]      Designof a CMOS 1 Mbit EPROM (27C210 - 64KX16), first set of photomasks (IC PhotomaskTapeout) released to production.[13]      Systemand logic design of a Virtual Instruction Processor, microcodedto emulate            the instruction sets of the Motorola 68020 and Intel 80386microprocessors.[12]      Systemand logic design of a MIL-STD-1553B remote terminal and controller, businterface            and protocol management unit.[11]      Logic,circuit design and IC layout of MIL-STD-1750A CMOS 16-bit microprocessor,            with FPU and interrupt controller for real-timeapplications.[10]      Designof mixed-signal, analog and digital CMOS IC for ordnance electronics. Low-power            watchdog and timer, integrated RF field rectifier and powermodule, filters, transceiver,            frequency and phase modulator and demodulator, polynomialcounters, and output conditioner.[9]        Designof a mixed-signal CMOS VLSI component for Rohm PBX equipment.[8]        Logicand circuit design and IC layout of bipolar SchottkyTTL, ECL and I3L IC cell            libraries, SRAM, F9450 microprocessor, high-speed businterface, timer and ADC[7]        Designand fabrication of CMOS IC and Si solar cells. Si process development:            photomasking, oxidation, dry andwet etching, ion implantation and thermal diffusion,            Al metallization. MOS devicecharacterization and modeling.[6]        Analogtest instrumentation, Automation of measurements using a DEC LSI-11/02            microcomputer, an ADAC-1000 data acquisition board and aGPIB-488 interface module.            System programming in Pascal, C and Assembly language.[5]        Designof a Gas Chromatography Controller, using an Intel 8748 Microcontroller, and            Analog Devices ADC.[4]        Prototypebreadboard and firmware development: test and calibration, sequencing, PID            control loop, data acquisition, formatting and display.[3]        Dataacquisition and control system for hydraulic pumps, using an HP9825,temperature,            vibration and pressure transducers and electronicmeasurement equipment. Application            program in BASIC.[2]        Characterizationand modeling of GaAs MESFET and microwave IC.[1]        Microfabricationand characterization of thin-film heterojunction GaAsInPlasers and            fiber-optics coupler. Liquid-phase epitaxy,photomasking and wet etching.EducationDiplome d'Ingenieur(BSEE MSEE)Ecole Superieured'Ingenieurs en Electronique et ElectrotechniqueParis, France - 1980.MSEEUniversity of Cincinnati, Ohio - 1981.Research work*    GaAs device modeling, digitaland RF analog circuits.*    GaAsInPsemiconductor laser.*    Data acquisition and electronic control circuits, Tin-filmCeramic Hybrid Circuit and FR4Printed Circuit Board, and system integration, automated product testing andcalibration.*    Si analog IC design andprocessing, semiconductor device manufacturing.*    Fabrication of MOS tunneldiodes and solar cells.Thesis: MOS Interface Trapped ChargeCharacterization Using The AC Conductance Technique MembershipInstitute of Electrical andElectronic Engineers (www.ieee.com), since 1979.Technology Alliance Bridge: www.tabridge.com, Silicon Valley, since1996.Other ActivityExpertAlpine Ski Instructor and Racing Coach, Auburn Ski Club (www.auburnskiclub.org).Contact us forconsulting, to bring you help and to work on your success.M: (530) 391-2978                    Skype:advlsi                    pierre@advlsi.com

TAGS:Integrated Circuits Electronics 

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