ASIC Standard Cell Library Design by Graham Petley

Time 2020-09-17 19:04:08

Web Name: ASIC Standard Cell Library Design by Graham Petley

WebSite: http://www.vlsitechnology.org

ID:50167

Keywords:

Cell,Library,ASIC,

Description:

This site contains support material for a book that Graham Petleyis writing, The Art of Standard Cell Library Design.This material includes standard cell libraries,which are made available under the terms of theGNU Lesser General Public Licence.There are no restrictions on using these libraries in an integrated circuit,and they can be copied, modified and distributed under terms of your choiceprovided that the original copyright is prominently displayed(see section 6 of the licence).Standard cell library informationThere are five new open source standard cell libraries, thevsclib,wsclib,vxlib,vgalib andrgalib.They have been drawn with theGraalsoftware fromAlliance,part of an extensive open source software suite for designing integratedcircuits with a standard cell design methodology.The libraries have been characterised in a generic 0.13 m technology.The spice model comes from theUniversity of California, Berkeley.The layout has been drawn usingMOSISlayer numbers and names and thepharosc rule set,and then scaledto what are slightly oversized 0.13 m rules which shouldbe compatible with most foundries.vxlib is compatible with thesxlibcreated by theAlliance software authors. Thevsclibis a completely new library design. Thewsclib is derived from thevsclib. Thergalib andvgalibare small gate array type libraries.Alliancesxlibhas also been characterised in 0.13 m using the same methodologyand converted to the same 0.13 m layout rules.There is also anssxlib which is theAlliancesxlibconverted with a script from 1 m to 2 m layout and adjusted toobey DSM layout rules. The adjustments change the timing slightly.The characterisation methodology creates aweb data book, and thisis on-line with the cells' layout and schematics.Recent releasesIn Release 8.1, thewsclib andssxlibhave been added. There are variantscalled stxlib, vtxlib, vtclib and wtclibwhich allow routing on the metal-1 level. See the examples directory in therelease file for more details.Release 8.2 has increased the size of thevsclib andwsclib,improving a number of the cell layouts and adding aDflip flop.Two small gate array libraries have also been added.Release 8.3 has added a latch to thevsclib andwsclib,and expanded the examples directory. Each cell's fixed delay in theAllianceVBEfile used for VHDL simulation has been set to the cell delay driving 25fF.Release 8.4 has some small corrections andhelp files for working from a Linux Live CD.Release 8.5 has much improved support forMagicincluding a single tech file, updated DRC files, completely revisedextraction parameters and extraction flow which avoids the previouskludge, andimproved colours for viewing the cells.Library development flowThe library development flow usesGraalfor the layout entry, andS2rto convert the layout to aCIF file. TheCIF file is read intoMagicwhich is used to extract aSpice deck and writeCIFGDS layout files.Magic has stronger features thanS2rfor converting layout drawings toCIF.The extracted spice decks are simulated withWinspice3using a0.13 mBSIM3model from the University of California, Berkeley.A comprehensive characterisation script is used,making it easy to add new cells.The transistor schematics for the libraries have been drawn withXcircuit,which uses Postscipt as its native file format.The characterisation results are formatted with scripts into aSynopsys Liberty .LIB format and anAllianceVBE format.Synopsys format is an industry standard, and the.LIBfiles use table lookup foraccuracy which matches or exceeds that of commercially available libraries. TheAllianceVBEformat allows the library to be used with theAllianceP R software,Ocp andNero, and simulated withAsimut.OCPfor place andNEROfor route need their source codemodified and then recompiled to use these libraries. Compiledversions made under Ubuntu 7.04 on Intel hardware are included inthe examples directory in the library release, and inhttp://www.vlsitechnology.org/binHelp pagesWeb pages offer help in downloading, viewing and characterisingthe cells.The Windows helpis for native Windows and for booting a Windows computer from a LinuxLive CD like Ubuntu 6.10 and 7.04. I don't use Windows much so I can't offermuch help on its use withAlliance. Frankly it isnot an operating system well suited to engineering work,more like a toy really, so a LinuxLive CD is a good option for Windows users.The Linux help is for users whohave Linux installed as their operating system.The libraries were first released on September 25, 2003,with a number of revisions since then.There is an extensiveREADME.txt file to help in using the library.The text files on this site have all been created on a Linux systemwhich uses LF for new lines. Windows uses CR LF ,and some Windows programs don't properly handle files using LF only.One of these isNotepad,the default viewer for TXT files.Wordpad allows these files to be viewed properly.In addition to the standard cell libraries, there is adiscussion of logical effort and how it hasbeen used for sizing the vsclib and vxlib transistors.There is a paper on supply line IR drop(33 pages) and how to size the power supplies to avoid problems.The paper onchoosing the cells in a standard cell libraryshows the benefits of adding cells to a library.Full details of the revision history are in therevision.txt file.Alliance synthesis paperSynthesis paper summaryA paper which shows how to achieve the fastest netlistsusing the Alliance synthesis toolsBOOM,BOOG andLOON.The sclib is used as an example, because it is ansimple library and has some limitations which need fixingto get the best synthesis results. The paper introduces somescripts which make it easy to get the fastest netlist.July 14, 2008IR drop paperIR drop paper summaryRead the paperon how to size integrated circuit power busesbased on the core power consumption and desired on chipIR drop. This is an extensive discussion of the topicrunning to 33 pages,which you won't easily find described elsewhere.Thoroughly revised on October 28, 2007A 10 page paper which analyses the vanGinnekenU.S. patent number 6,725,438at the heart of the dispute between Synopsys and Magma.A 4-bit adder using anopen source standard cell libraryis used as a real example to test the patent claims and measure themagainst prior art and a manual optimisation.Old now, dating from August 200536 pages documenting a methodology forchoosing which cells to include in a library.November 2006A brief survey of open source standard cell libraries which can be downloadedfrom the web. Updated on November 4, 2007.Discussion and proposal on which cells to include in a small standard celllibrary. Links to three other papers on the subject.Updated on April 26, 2006.A brief survey of software for IC polygon pushing layout which canbe downloaded from the web, and other programs forwhich you must pay money. Updated on October 30, 2007.This bash script will print a list of the unique functions that are possiblefor cells with 1,2,3 or 4 inputs.WinSpice3 is theSpiceprogram used to characterise the libraries on this web site.It works in both Windows and Linux withcodeweavers and wine.Free download, very cheap registration,powerful control statements,BSIM3 support and excellentdocumentation. You'll probably need it to run theSpicecharacterisation routines in the library download file.Steve Golson has won many Best Paper awards at SNUG Conferences.His papers and some scripts are gathered on this page.The paper on wireloads from SNUG 1999 is particularly good.reference book on logical effortThe book on Logical Effort by Ivan Sutherland, Bob Sproull and DavidHarris is strongly recommended. This web site has some supportinginformation. You can also read mydiscussion on logical effort.

TAGS:Cell Library ASIC 

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vlsitechnology.org has a downloadable standard cell library, the vsclib, with full scripts for cell characterisation in a generic 0.13um technology. A web databook helps in reviewing cells.

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