VLSI Basics And Interview Questions

Time 2020-09-25 22:14:25

Web Name: VLSI Basics And Interview Questions

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check_library validates the libraries i.e., it performs consistency checks between logical and physical libraries, across logical libraries, and within physical libraries.This command checks library qualities in three main areas:Physical library qualityLogic versus physical library consistencyLogic versus logic library consistencyPNR tool wont optimize the paths which are not constrained. So we have to check any unconstrained paths are exist in the design. check_timing command reports unconstrained paths.If there are any unconstrained paths in the design, run the report_timing_requirements command to verify that the unconstrained paths are false paths.report_constraintsIt reports to check the following parameters.Worst Negative Slack (WNS)Total Negative Slack (TNS)Design Rule Constraint ViolationsThe report_timing command provides a report of timing information for the current design. By default, the report_timing command reports the single worst setup path in each clock group.report_qor:report_qor displays QoR information and statistics for the current design. This command reports timing-path group and cell count details, along with current design statistics such as combinational, noncombinational, and total area.The command also reports static power, design rule violations, and compile-time details.check_design:check_design checks the current design for consistency.The check_design command checks the internal representation of the current design for consistency, and issues error and warning messages as appropriate.Error messages indicate design problems of such severity that the compile command does not accept the designWarning messages are informational and do not necessarily indicate design problems. However, these messages should be investigated.Potential problems detected by this command includeUnloaded input ports or undriven output portsNets without loads or drivers or with multiple driversCells or designs without inputs or outputsMismatched pin counts between an instance and its referenceTristate buses with non-tristate driverswire loops across hierarchies, and so forth.Here I am going to discuss about Tie Cells Insertion. Before going toknow about Tie Cells Insertion, We have to know what Tie Cells are. Tie Cells:Tie cells are special purpose standard cells whose output is ConstantHigh or Constant Low. These cells are used to hold (tie) the input of othercells which are required to be connected Constant High (Vdd) or Constant Low(Vss) values.Tie High Cell:Tie High Cell is special purpose standard cell whose output is ConstantHigh (Vdd).Tie Low Cell:Tie Low Cell is special purpose standard cell whose output is ConstantLow (Vss).There are some unused inputs in thedesign netlist. These unused inputs should not be floated. They should be tiedto either Power (Vdd) or Ground (Vss). The inputs which are required to connectVdd, connect to Tie High cells. The inputs which are required to connect Vss,connect to Tie Low cells. This is the purpose of Tie cells in the designWhy Tie cells are inserted? In lower technology nodes the gateoxide of the transistor is so thin and sensitive to voltage fluctuations in thepower supply. If the gate of the transistor is directly connected to thePower/Ground network (Power Grid Network), the gate oxide of the transistormight be damaged due to voltage fluctuations in the power supply. To overcomethis disadvantage, Tie cells are inserted.To perform Placement Optimizationor Physical optimization, Automatic Insertion and Optimization of Tie offs arerequired in the design. The following commands are used to execute the same.set_auto_disable_drc_nets-constant falsephysopt_new_fix_constants trueset_attribute [...]max_fanout 12set_attribute [...] max_capacitance 0.2-type floatTie-off Optimization:Tie cells optimization means usinga tie cell to hold (tie) as many inputs as possible at given logic level, whilemeeting specified maximum Fanout and maximum capacitance constraints (LogicalDRCs). The set_auto_disable_drc_nets command enables DRC on constant nets.The set physopt_new_fix_constantsvariable to true causes placement toolto observe the maximum capacitance constraint during tie-off optimization.maximum capacitance constraint is determined by the max_capacitance attribute,which can be set with the set_max_capacitance or set_attribute command.The set_attribute command can be used to specify explicitly boththe maximum fanout and maximum capacitance constraints for objects in thedesign.Note:We can also insert tie cells manually with thecommand connect_tie_cells. Thecommand inserts tie cells and connects them to specified cell ports, whilemeeting maximum fanout and maximum wire length specified in the command.Here let us discuss about congestion. What is Congestion? What are the reasons for Congestion? How congestion can be fixed?What is Congestion?If the number of routing tracks available for routing in one particular area is less than the required routing tracks then the area said to be congested. There will be a limit for number of nets that can be routed through particular area.What are the reasons for Congestion?Bad floorplanDuring IO optimization tool does buffering, So lot of cells placed in the core areaIf the congestion is not too severe, The actual route can be detoured around congested area. The detoured nets will have worse RC delays than actual VR estimates.If the congestion is too severe, the design can be un-routable. This is really not good. It is important to minimize or eliminate the congestion before continuing.Rerun the fast placement with Congestion driven option (Congestion driven placement)Modify physical constraints such as adjust cell density in congested areas. Because higher cell density cause for congestion.Use/Modify proper blockages. i.e., Soft blockages, Hard blockages, Macro Padding are used proper locations to minimize the congestion near macros.Modify floorplaning such as moving macros, change core shape/size, Move pins to give enough room for routingAs discussed earlier, Congestion driven placement is performed to reduce the congestion. During congestion driven placement, the cells (Higher cell density) which caused for congestion are spread apart. If the cells along timing critical paths are spread apart to minimize congestion, What happens?If the cells along timing critical paths spread apart, the timing constraints along that particular paths are not met which cause for timing violations. But these violations can be fixed during incremental optimization.What are the care should be taken using congestion driven option?If there is some congestion, use medium effort optionIf the congestion is bad, use high effort optionIf there is no congestion, Don't use congestion driven option. If we use congestion driven option in this case, It takes more rum time for placement.As discussed earlier, Higher cell density can cause for congestion. By default the cell density can be upto 95%. We can reduce the cell density at congested areas by using coordinate option.As shown in below figure, we can set cell density to a flexible number to reduce the congestion by using the commandset_congestion_options - max_util 0.6\ - coordinate {x1 y1 x2 y2}Here we set the maximum cell density upto 60% and given the coordinates for the particular area.How blockages and macro padding(Halos) reduce congestion?By using blockages and halos, They prevent the tool placing cells in that particular locations to give enough space for routing near the macros. For more details, please refer Blockages halos post.Soft Blockages created only for the channels between macros (or) Between macro the core boundary to give enough space for routing.Hard blockages always created on the four sides of macro for not to place standard cells or macros near to the macro.Macro Padding: If the design contains macros that are not placed near another macro (or) the edge of the core then macro padding(Halo) is created. Standard cells cant be placed in this region which give more routing resources to the signal routes.Before going to discuss about we have to know the basic terminology like What is Fanout? What are High Fanout Nets (HFN)? Why we are going for High Fanout Net Synthesis (HFNS)?What is fanout?Fanout is the number of gate inputs to which the output can be safely connected. i.e., The load that a gate output can drive. The maximum fanout of an output measures it's load-driving capability. Fanout belongs to the output.What are High Fanout Nets(HFN) ?High Fanout Nets are the nets which drive more number of load. We set some max fanout limit by using the command set_max_fanout. The nets which have greater than these limit are considered as High Fanout Nets (HFN). Generally clock nets, reset, scan, enable nets are High Fanout Nets.What is High Fanout Net Synthesis (HFNS)?High Fanout Net Synthesis (HFNS) is the process of buffering the High Fanout Nets to balance the load.Why HFNS?To balance the load HFNS is perfomed. Too many load affects delay numbers and transition times. Because load is directly proportional to the delay. By buffering the HFN the load can be balanced. This is called as High Fanout Net Synthesis(HFNS).Where HFNS ?Generally at placement step HFNS performed. HFNS can also be performed at synthesis step using Design Compiler. But it's not good idea, Buffers will be removed during PD and again HFNS is performed. It's very time consuming process. So HFNS at synthesis step is not recommended. HFNS atsynthesis step gives an idea whether HFN are present in data path or not. Generally HFN are present in clock paths, rest, enable and scan paths.Care that should taken during HFNS:1. Make sure an appropriate fanout limit is set using set_max_fanout command2. Verify the SDC used for PD should not have set_ideal_network or set_dont_touch commands on High Fanout Nets.3. Use ideal clock network - As clock nets are synthesized separately during Clock Tree Synthesis (CTS) step, we set clock network as ideal network.NOTE:As clock nets are considered as ideal, buffering is not performed on the clock nets even they are High Fanout Nets. So, HFNS is the process of synthesizing other than clock nets, such as reset, scan, test enable nets is called as High Fanout Net Synthesis (HFNS)Level Shifters, Isolation Cells, Retention Registers, Power Switches, Always on CellsLevel Shifters:Level Shifters are used in multi voltage design in which more than one voltage supply used. Consider In your design two voltage domains are there. One voltage domain V1 has 1.2V power supply another domain V2 has 1V power supply. Signal has to cross from one domain to another domain while in functional mode. Now assume signal crossing from Low voltage domain V2 to High voltage domain V1, It's logic is interpreted wrongly at V1. To prevent this level shifters are inserted between the different voltage domains for the signals which cross from low voltage domain to High voltage domain and from High voltage domain to low voltage domains.The main functionality of the level shifters is to shift the voltage one voltage to another voltage level depending upon the the signal crossing different voltage domains.Isolation Cells:Isolation cells are used between the domains. Consider there are two domains are in your design i.e,. D1 and D2. The domain D1 is power shut down mode and other domain D2 is in active mode. Since Domain D1 is power down mode it can propagate invalid logic to domain D2. To prevent this, Isolation cells are inserted between the domains to clamp a known value at its output, While domain D1 is shut down mode. Isolation cells should be placed in always on domain to serve it's functionality (clamp the known value to the other domain)Power Switches:Power switches are used in power gating technique. As we alreadydiscussed in previous post, Power gating is used to reduce the static (Leakage) power in the design. Power gating is performed by shutting down the power for portion of design. Power switches are used to turn off the portions of design which are inactive at a point of time to reduce leakage power.Retention Registers:Retention Registers are used to store register states before power down mode. These values will be restored when power is up. So retention cells should be always on to serve the purpose. As these are always on, It can consume power even power down mode.Always On cells:These cells are special cells which should be always on to their purpose.The general ICC flowis as shown in figure 1. The first step in ICC Flow is Data Setup. Inthis step, we create Container which is known as Design Library . The inputs which are required for physicaldesign are loaded into this Design Library.i.e., The Design Library contains Logical/Timing Library files, PhysicalLibrary Directories, Constraints, Gate-level Netlist, Technology File, RC(TLU+) Model Files. We provide these Design Library as input to the ICCompiler. The output of the IC Compiler will be Placed, Routed and Optimizedlayout with Clock Trees as shown in below figure 2.Inputs forICC Physical Design Flow:As shown infigure 2 the inputs for ICC Physical Design flow are logical/Timing libraries,Physical libraries, Technology file, Design Constraints, Gate Level Netlist, RC(TLU+) Model Files. These are given to the ICC tool. Here I am going to discussabout these inputs. Figure 2Inputs and Outputs ofICC FlowLogical Libraries are library files whichprovide timing and functionality information of each and every standardcells (AND, OR, Flipflops etc) used in the design. It also provides timinginformation of hard macros such as IP, ROM, RAM etc. Logical Libraries defineand load the Logical DRC such as Maximum fanout, MaximumTransistion, Min/Max Capacitances. Logical libraries are also used atSynthesis step in DC. These are in .db form. Logical libraries are specified bythe variables target_library and link_library.2. Physical/ReferenceLibraries (Milkyway .db):Physical/Referencelibraries contain Physical Information of standard, macro and pad cells, whichis necessary for placement and routing. These libraries define placementtile (Height of placement rows, minimum width resolution, preferred routingdirection, Pitch of routing tracks etc). These libraries are specified withcommand create_mw_lib mw_reference_library.Technology file:A Technologyfile is provided by the technology vendor. Technology file is unique for eachtechnology. Technology file contains the information related to metal/viainformation such as Unitsand precision for electrical units (Voltage,Current, Power etc) Definecolors and patterns of layers for display Numberand Name designations for each metal/via Physicaland Electrical characteristics of each metal/via DefineDesign rules such as minimum wire widthsand minimum wire to wire spacing ContainsERC rules, Extraction Rules, LVS rules Provideparameterized cells (PCELLs) for MOS, caps etc Createmenus and commands (Ex: create contact)4. RC (TLU+)Model:ICC calculates delay forevery net and every cell. To calculate delay tool needs each net R s and Capacitances.IC Compilercalculates interconnect R and C values using net geometry and TLU+ look uptables. It models UDSM process effects. TLU+ is a binary table which has R and C values for delay calculation.It can be intheformof Verilog or VHDL(.v or,vhdl). This netlist is produced during logicalsynthesis, which takes place prior to the physical design stage.6. Constraints:Design constraints (like system clock definitionand clock delays, Multiple cycle paths, Input and output delays, Minimum andmaximum path delays, Input transition and output load capacitance, False paths)are identical to those which were used during the front-end logic synthesisstage prior to physical design. It is available in the form of SDC (SynopsysDesign Constraints). Unit 03, No 65/2Bagmane Tech, Byrasandra in Ward no. 83, Bangalore, Karnataka, India 4 Floor, Block B, BrigadeTech, Pattandur Agrah Villg Whitefld, Bangalore, Karnataka,India ITPL Rd, Site 6/2 6/3, 4Flr, A/B Wing Thoobarahalli Village, Bangalore, Karnataka, India Discover Bldg, Unit 1,10/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka,India Inventor Bldg, Unit1 2, 5/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka, India Navigator Bldg, Unit1 2, 7/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka,India Innovator Bldg, 1/Fl, Int'lTech Park, Whitefield Rd, Bangalore, Karnataka, India DevarabisanahalliVillage, Sarjapur Ring Road, Bangalore, Karnataka, India 3rd Flr Tower A, PlotC28 29, Sector 62, Noida, Uttar Pradesh, IndiaPhone :080-22869330. FAX : 080-22867431Area :Microprocessors, Network Processors, DSP Processors, Switching, EmbeddedProcessors.Skill : VHDL/Verilog, VLSI Design, ASICDesign, Architecture, Testing/DFT/BIST.Adarsh Eco Place, 176, EPIP Zone, Phase II, Whitefield, KundalahalliHobli, KR Puram Taluk, Bangalore, Karnataka 560066, India.Plot Nos 125-127, EPIP, Phase II, Whitefield, Bangalore,Karnataka 560066, India.Plot No131, Sonnenahalli Village, EPIP Phase II, Whitefield,Bangalore, Karnataka 560066, India.Building No 2 B, 9th Floor, Maximus Towers,Mindspace Complex, Hyderabad, AP 500081, India.Building No8, Floors 1,3,4,5, Mindspace, Hitec City Road,Madhapur, Hyderabad, AP 500081, India.Area : CDMAWireless Communications, 3G Chip Sets, Library Development.Skill : VLSI Design, ASIC Design, DSPArchitectures, Physical Design, DFT, Verification, VHDL/Verilog.3. BrodcommCampus 3A, 5thFloor,RMZ Eco Space,Global Technology Park, Block-C, Marathahalli Outer RingRoad, Devarabeesanahalli, Bangalore 560 103, Karnataka, India3rd and 4th Floor, Building #4, Commerzone, Survey, 144,145,Samrat Ashok Path, Off Airport Road, Yerwada, Pune, Maharashtra, India 411 006Phone:+91-020-40104700Fax:+91-020-401047016. ST Micro ElectronicsIndia DesignCentre,Plot no. 1,Knowledge Park III,GREATER NOIDA --201 308.Phone :0120-2352999.FAX : 0120-2569497.Area : Consumer, Memory, Standard Products,Technology Library, Peripherals,IndustrialControl, Imaging, Multimedia.Skill : Analog, Mixed-signal, PhysicalDesign, VHDL/Verilog, Architectures, DFT, Formal Verification, Scripting.7. Texas InstrumentsBagmane TechPark,C. V. RamanNagar, Bangalore 560093.Phone :080-25345454, 25345455.FAX : 080-25048213.Area : DSPProcessors, Memory, PCI, 3G Wireless.Skill : VHDL/Verilog, VLSI Design, CADTools, RF Design.8. ST EricssionStreetaddress:Ericsson Forum DLF Cyberciti Extended address:Sector-25ALocality:Gurgaon Haryana Postal code:122 002 Country:IndiaPhone:+91 1244151201 Phone:+91 124 4151001 Fax:+91 124 25654549. AMD (Advanced Micro Devices)AMD India Pvt Ltd.#102-103, Export promotion Industrial Park,Whitefield, Bangalore-560066Karnataka, IndiaTel: +91-80-332-30000Fax:+91-80-332-30555AMD Research Development Ctr. India Private LimitedMindspace - CyberabadAPIIC Software Layout,8th-11th Floor,Building No: 11,Madhapur, HyderabadAndhra Pradesh-500081 IndiaTel: +91 40 3061 500010. ARMLevel III,Salarpuria TouchstoneMarthahalli-SarajapurOuter Ring Road,VarthurHobli, Bangalore-560103Contact DetailsTel. +91 80 25185000 Fax +91 80 2844Will be continued......A. The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current start flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. This Drop is called as IR Drop. For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this context can allow upto 0.4 volts drop which does not effect the timing and functionality of design. The process of analyzing this IR Drop is called IR Drop Analysis.2. What are the different types of IR Drop Analysis?A. There are two types of IR Drop Analysis 1. Static IR Drop Analysis 2. Dynamic IR Drop Analysis Static IR drop Analysis is vectorless power analysis with average current cycles, whereas, Dynamic IR drop analysis is vector based power analysis with worst-case switching currents.3. What are the different tools used for IR Drop Analysis?A.Various tools are available for IR Drop Analysis. Voltagestorm from Cadence, Redhawk from Apache are mainly used to show IR Drop on chip.4. What are the different reasons for high voltage drop in a design?A. In a design if there is high static or dynamic voltage drop, It could be due to one of the following reasons.High current flowing through the power grid : can affect Static as well as Dynamic IR dropHigh PG grid impedance : can affect static as well as Dynamic IR DropSimultaneous Switching : can affect only DynamicInsufficient number of voltage sources : can affect Static as well as Dynamic DropHigh Package parasitics : can affect Static as well as Dynamic DropInadequate amount of Decaps available : Can affect only Dynamic5. How to find the high IR Drop analysis is due to high current flowing through the power (PG) grid?A.IR Drop is Signal Integrity(SI) effect caused by wire (metal) resistance and current drawn off from Power (Vdd) and Ground (Vss) grids. Static or Dynamic IR Drop is proportional to the current flowing through the power grid. High average current can cause for high Static IR Drop. Similarly in dynamic analysis, high transient(switching) current can lead to high Dynamic IR drop.Average current is proportional to the average power of the design. High average power canaffect both static and dynamic voltage drop results. Redhawk power summary report file (adsRpt/power_summary.rpt) will give you the details of power consumption of the design. Power summary report will give you the power consumption for each voltage domain, frequency domain and for each cell type in the design.Instance power file (adsRpt/ design .power.rpt) will contain instance specific power values. Youcan also click on any instance in the GUI to get more details of power calculation for that instance.In Redhawk GUI, you can see the sorted list of high power instances in the design using Results- List of Highest Power Instances for Static Simulation menu.You can use the Power Density map (PD) (in figure2) to get the power density distribution in the design. Similarly, Instance power map (IPM) will show you the instance power distribution. Similarly, clock power map (CPM) will show power distribution separately for clock related instances in the design. Figure2. Redhawk Home page GUI(Source : Apache Redhawk Tool)Average power has both static and dynamic components. Static component is the leakage power.You can look at the leakage power map (LPM) in the results panel (figure2) to see whether there are any cells with excessive leakage.From the instance power file (adsRpt/ design .power.rpt) you can find leakage power component for any instance.Dynamic component is contributed by internal power and the switching power. This component isproportional to the frequency, load and toggle rate. Reason for high dynamic power could be oneof the following:High Load capacitance.High toggle rate or BLOCK_POWER_FOR_SCALING used in the analysis.You can analyze the Instance Frequency Map (IFM) to see whether high frequency is causing high power in some region.Load Cap map (LC) will tell you whether high load is causing the dynamic component of power. High load issue normally happens when you have un-synthesized clock tree or scan chains, with some buffers driving huge fanout load.High toggle rate can also cause high dynamic power. Redhawk derives the toggle rate from one of the following ways.User can scale the power values computed by scaling the TOGGLE_RATE using theGSR keyword BLOCK_POWER_FOR_SCALING. Values specified in this section directly affect your static and dynamic results.You can also click on any metal / via segments to see the amount of current flowing through the geometry. Static analysis shows the average current and dynamic analysis shows peak current. In static analysis, it will also show you the current direction. CUR Map shows the current distribution throughout the chip.High transient current can be caused by simultaneous switching in the design.6.How to find the high IR Drop analysis is due to highPG impedance?A.High Power grid resistance will impede the current flow in the power grid causing high static or dynamic voltage drop. You can use PG Resistance Map (View - Resistance Maps) to highlight areas with high PG resistance. Also, you can write out the PG Resistance report using the Redhawk command perform gridcheck . More details on PG Weakness analysis can be found in the application note Analyzing PG Weakness Results in Redhawk GUI .Redhawk has several features to analyze the structural weakness issues in the power grid. Youcan use View - Connectivity menu to analyze PG structural issues such as:When you highlight disconnected instances in Redhawk GUI, instances with VSS disconnect will get highlighted in Blue, VDD disconnect will get highlighted in Green and both VDD/VSS disconnect will get highlighted in Yellow. Corresponding text reports are also available inside adsRpt directory (adsRpt/*.unconnect, adsRpt/apache.missingVias etc).If there is any major disconnect in the power grid, it will affect the current flow in the design. You can use the current map (CUR button) to review the current flow through the power grid to see whether there are any surprises.If you are performing RLC extraction on the power grid, high inductance can also cause high dynamic drop. You can perform a dynamic analysis based on RC extraction and compare the results to see whether L component is causing the high drop.References:1. Redhawk User's Manual by Apache Design AnalysisStatic Voltage (IR) drop with average cycle currentsDynamic Voltage drop with worst-case switching currentsElectromigration (EM) AnalysisCritical path and clock tree impactsAs discussed above Redhawk is used to perform EM, IR and transient analysis on power grid. Redhawk is available in different modes. They are1. Static Mode2. Dynamic Mode3. Transient Mode1. Static Mode:In static mode, Redhawk can perform EM, IR drop analysis. In this mode the tool analyzes average IR Drop and EM in the design.2. Dynamic Mode:In Dynamic mode, Redhawk analyzes peak IR drop in the design during functional mode using Vectorless algorithm or VCD. It can also analyze peak IR drop in the design during scanning mode using Vectorless or VCD.3. Transient Mode:In Transient mode, Redhawk can perform power up and power down analysis. It analyses peak rush current during turn-on, power grid turn-on time.Inputs for Redhawk :. LEF. DEF. LIBS. TECH. ploc. GSR. DSPF/SPEF. design .timingAPL files ( cell.spcurrent, cell.cdev)This is a industry standard format that has the information related to pin description and boundaries of the block /instances in the design.DEF - Design Exchange Format :This contains logical and physical connectivity between different instances and blocks in the design.LIB - Synopsys liberty format:This has several electrical and logical properties for a cell like: input and output pin properties, information on distributing power among the different power pins, internal energy of the cell, cell functionality information, etc.SPEF - Standard Parasitic Exchange Format:This file contains the parasitic (RC values) associated with each nets in the design.ploc:It containsPad location information based on Full-chip Floorplan.Redhawk Tech file:It containsResistance information for all interconnect layers,EM limit information for all interconnect layers,Interconnect Stack information.APL Files:ItContains Current Profile characterization data for each standard cell,Intrinsic decap characterization data for each standard cell,Piecewise linear cap characterization data for each standard cell. design .timing:It containsSTA Timing Information From Primetime. It isRecommended for Static analysis-provides accurate transition times and instance frequency. It required for Dynamic provides switching windows.RedHawk outputs: IR voltage drop contour maps Electro-migration (EM) analysis Power density and average current maps Text report files of detailed static power, voltage, and current data Warnings and violations reports.You Might Also Like:Physical Design (PD) Interview Questions - Floorplanning 1. What is floorplaning? A. Floor planing is the process of placing Blocks/Macros in the chip/core area, thereby determining ...IR Drop Analysis What is IR Drop Analysis? How it effects the timing? The power supply in the chip is distributed uniformly through metal layers (Vdd a...Clock Tree Synthesis (CTS) - Overview Clock Tree Synthesis Clock Tree Synthesis (CTS) is the process of inserting buffers/inverters along the clock paths of the ASIC design to...Blockages and Halos BLOCKAGES: Blockages are specific locations where placing of cells are prevented or blocked. These act as guidelines for placing std cel...IR Drop Analysis using Redhawk - Overview IR Drop Analysis using Redhawk: Redhawk performs several types of power analysis on a circuit. Static Voltage (IR) drop with average c...Sanity Checks in Physical Design Flow Sanity Checks in Physical Design Flow check_library check_timing report_constraint report_timing report_qor check_design c...

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