SemiWiki - All Things Semiconductor!

Time 2020-10-05 08:03:12

Web Name: SemiWiki - All Things Semiconductor!

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[queried_object_id] => [request] => SELECT SQL_CALC_FOUND_ROWS wp5_posts.ID FROM wp5_posts WHERE 1=1 AND wp5_posts.post_type = 'post' AND (wp5_posts.post_status = 'publish' OR wp5_posts.post_status = 'expired' OR wp5_posts.post_status = 'tribe-ea-success' OR wp5_posts.post_status = 'tribe-ea-failed' OR wp5_posts.post_status = 'tribe-ea-schedule' OR wp5_posts.post_status = 'tribe-ea-pending' OR wp5_posts.post_status = 'tribe-ea-draft') ORDER BY wp5_posts.post_date DESC LIMIT 0, 10 [posts] => Array [0] => WP_Post Object [ID] => 291504 [post_author] => 23 [post_date] => 2020-10-04 10:00:41 [post_date_gmt] => 2020-10-04 17:00:41 [post_content] => The first warning sign was “hackproof” in the 360Lock marketing materials. As it turns out, with no surprise to any security professional, the NFC and Bluetooth enabled padlock proved to be anything but secure.Straightforward penetration testing revealed horrible logical and physical security for a padlock that promotes itself as “incorruptible” and “hackproof”!Digital Transformation is a rush to connect our physical world to the global electronic ecosystem to enable better access, integration, and advanced capabilities. Internet of Things (IoT) devices are often at the forefront of this movement, turning normal devices into ‘smart’ devices. Sometimes even the best ideas fail when it comes to design and execution.This padlock has several innovative features such as connectivity to mobile applications, an included RFID wristband and tag for easy unlocking, configurability to add access for others, and a detailed history log. What it lacks however, is actual security.Security theaterSimple pentesting proved what was likely a foregone conclusion. The kickstarter funded lock is neither hackproof nor secure. Testers found that simple replay attacks could trick the logic to open the device. Additionally, crude brute-force methods were able to compromise the integrity of the lock mechanism. Pounding it with a hammer quickly defeated the padlock.The results highlighted that the $40 lock is not robust and better served as a visual deterrent, casual locking device, or novelty item.An industry problemA massive quantity and vast diversity of smart devices are emerging. Most connect to the internet and require a high degree of security. Connectivity accentuates vulnerabilities. Sadly, many of the IoT devices consumers and businesses are embracing lack the necessary measure for security rigor, leaving users exposed and data vulnerable.The 360Lock is not the only device that has poor security, but it does highlight two important points, emphasizing overall industry challenges.First, never trust any product that claims to be ‘unhackable’. Seasoned security professionals would never make such an outlandish assertion as to say a device is hackproof! The fact that 360Lock promoted their product in this way was the only indicator needed to instill great skepticism.Second, this device’s weaknesses highlight the need for proper data transport security. Man-in-the-Middle (MitM) attacks, such as a replay attacks, are common tactics for hackers. Transactional security is absolutely critical to protect data and requests. Unfortunately, securing data in-transit between IoT devices on the edge and phones/PC/cloud-services requires the right expertise and tools. Most failures occur in how data protections are implemented and managed. As a rule, if a product manufacturer is not detailing their security, they likely do not have quality capabilities in place.Painful lessonsConsumers must be wary and realize that even dedicated security products, such as padlocks, can be victimized by poor development decisions. Trendy features are no replacement for solid security and reliability. IoT devices are often much less secure than the marketing materials and salesperson will reveal. Look for reputable manufacturers who have committed to work with the best technology, security integrators, and verification practices. Every consumer and business is responsible for understanding the risks accompanying the benefits of new technology.Interested in more? Follow me on LinkedIn, Medium, and Twitter (@Matt_Rosenquist) to hear insights, rants, and what is going on in cybersecurity. [post_title] => Painful IoT Security Lessons Highlighted by a Digital Padlock [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => painful-iot-security-lessons-highlighted-by-a-digital-padlock [to_ping] => [pinged] => [post_modified] => 2020-10-02 14:15:31 [post_modified_gmt] => 2020-10-02 21:15:31 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291504 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [1] => WP_Post Object [ID] => 291517 [post_author] => 19 [post_date] => 2020-10-04 08:00:03 [post_date_gmt] => 2020-10-04 15:00:03 [post_content] => Uber Technologies won’t be reporting its latest earnings for another month, but when it does so in November the news is not expected to be good. In an effort to flip the script in advance of that report and distract attention from the ongoing COVID-19-induced decline in its core ride hailing business, Uber has launched Uber Green – a global effort to situate Uber at the center of an environment-saving shift to vehicles with electrified powertrains.Uber White Paper: Spark! Partnering to Electrify in Europe - https://d1nyezh1ys8wfo.cloudfront.net/static/PDFs/Uber_Spark_report.pdf?uclick_id=9d04acd6-f912-4cec-b11d-20bef0aa7f46By now, it’s clear that Uber will do whatever it takes to survive – everything, that is, but the right thing. Uber has yet failed to implement a partition deployment proposition to adequately protect drivers and passengers during the pandemic.The Uber Green effort (in Europe) is comprehensive and includes driver and passenger incentives – to drive and ride in electrified Uber’s where available – along with auto maker incentives for Uber drivers to acquire and use vehicles with electrified powertrains, coordinate with charging network operators and municipal authorities to foster the use of EVs and hybrids, and collaborate with regulators over Uber-derived data for the sourcing and installation of charging stations and enhanced carrot-and-stick policy making.This a very different tune for Uber to be singing after former founder Travis Kalanick’s claims from six years ago that Uber would eliminate car ownership and public transportation. With ride hailing volume cut in half globally, Uber comes hat in hand to both car makers and public authorities – a wolf in sheep’s clothing – offering to help speed the adoption of cars with electric powertrains.Uber CEO Dhara Khosrowshahi brings gifts in the form of research and data to help European cities expand their zero emission policies. For drivers he brings 50 cent and $1/ride subsidies (with annual limits) and a battery of research (in the related white paper above) describing the ways in which Uber driving in an electrified vehicle can be financially justified over a new or used diesel or internal combustion vehicle.Yet, at the same time, Uber acknowledges that the financial proposition of actually acquiring an EV or hybrid to drive for Uber is no guarantee of financial success. Uber knows its drivers will need generous incentives to justify such a shift.SOURCE: Uber Green white paperBeyond that, Uber’s cynical siren song glosses over the reality that the company controls driver compensation. So, Uber may provide a minor per-ride subsidy while adjusting driver compensation or, heaven forbid, benefits, downward elsewhere. Uber Green is a bait and switch.Worse than a bait and switch, though, Uber Green is a cynical effort by Uber to use its global leverage to muscle its way into the policy-making activities of major municipalities and thereby worm its way to the front of the line for accessing prejudicial regulatory treatment. To do this, Uber is painting itself Green and ingratiating itself with environmental groups and organizations in an attempt to gloss over its history as a very unfriendly industry participant with a history of abusing its non-employees, undermining existing transit options, and flouting regulations.Uber Green is a grift and no one, least of all car makers or municipal leaders, should be deceived that Uber will do anything other than what is best for Uber – even if it means mistreating drivers, passengers, competitors, or regulators. It wasn’t long ago that Uber was hacking regulators and competitors and failing to adequately check the backgrounds of its drivers.There is one unmitigatedly positive thing that Uber could do to transform its reputation and financial prospects. Uber could launch a global effort to make partitions available on a widespread basis to its non-employee drivers and require the installation of those partitions. Uber’s failure to take this step while sitting on billions of dollars in investor cash is an enduring travesty worthy of Travis Kalanick’s legacy. It’s time for Dhara Khosrowshahi to finally put his stamp on the company and make a statement for driver and passenger safety. In the absence of this step, Uber’s ride hailing revenue won’t recover for another 12 months or worse. [post_date_gmt] => 2020-10-04 13:00:36 [post_content] => At the recent TSMC OIP Ecosystem Forum and Technology virtual events, TSMC re-affirmed their previous prediction that 5G is going to be a multi-year silicon mega-trend with the biggest drivers being the ramp up of 5G handsets, supporting infrastructure and the continued growth of high performance computing (HPC).We all want the luxury of live streaming, whether it be a concert or sports event, playing the latest games or watching HD movies on our phone, but what is it that actually allows 5G ASIC designers to deliver this enhanced level of user experience? Today’s Semiconductor advanced node technology really is the beating heart of 5G network technology.  Powering network base stations, cars, smartphones, and other connected devices, but 5G also plays an integral part of a much bigger technology phenomenon…Hyperscaling.5G infrastructure is extremely power hungry and generally requires ~3 times the number of base stations compared to older technologies such as LTE, due to the higher frequencies involved. Moortec is already working with customers in the 5G space to help address some of these infrastructure power issues.5G Silicon Challenges5G enabled devices such as handsets, tablets and wearables have certainly helped revitalize the consumer electronics space as they have moved from typically planar nodes down to FinFET process technologies like 5nm.This step change does however present designers with specific challenges, one of the biggest being increased thermal activity associated with the data intensive workloads associated with the system​. Battery life can also be an issue when running 5G and associated applications like video, and gaming etc. If the thermal conditions are not carefully monitored and controlled, handsets may either switch to a lower power 4G mode or even turn off altogether. As a user why do I care? Well, apart from the handset becoming noticeably warmer to the touch, your video download will take longer or freeze and your phone will need recharging more frequently as the battery will drain faster.A 5G small cell can be operational for over a decade in potentially hostile environments, without any forced air cooling and as such it is particularly important to be able monitor them remotely in the field.Moore’s LawIn the last instalment of the Moortec ‘Talking Sense’ blog my colleague Tim Penhale-Jones talked about the impact that Moore’s law and Dennard Scaling have had on the advanced node semiconductor sector. For some time, we have been cramming ever increasing amounts of processing power into each 1mm2 of silicon and this has enabled the 5G technology that we see emerging today. However, the pressure continues to Miniaturize (device size), Maximise (power performance) and Optimize (reliability battery life) and in order to continue to do this successfully it is critically important to understand the dynamic conditions within the device itself.Benefits of In-Chip Monitoring for 5G DevicesBy implementing highly configurable, real time embedded sensing fabrics, chip designers can address some of the challenges associated with overheating, reduced data throughput and diminished battery life. This enhances the overall user experience in consumer products like 5G handsets and increases the performance optimization and reliability of infrastructure devices in the field.To find out how Moortec’s in-chip monitoring technologies and sensing fabrics could benefit your next advanced node 5G project contact us today.In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE. [post_title] => 5G, Hyperscaling and the Resurgence of Consumer Silicon [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => 5g-hyperscaling-and-the-resurgence-of-consumer-silicon [to_ping] => [pinged] => [post_modified] => 2020-10-04 11:04:43 [post_modified_gmt] => 2020-10-04 18:04:43 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291449 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [3] => WP_Post Object [ID] => 291492 [post_author] => 28 [post_date] => 2020-10-02 10:00:16 [post_date_gmt] => 2020-10-02 17:00:16 [post_content] => The semiconductor industry has never been more exciting than it is today and that is a mouthful given what we have accomplished over the last 50 years. From mainframe computers to a supercomputer in our pockets or on our wrists. Even if you don’t believe in miracles, semiconductor technology comes really close, absolutely.U.S. tightens exports to China's chipmaker SMIC, citing risk of military use REUTERSWhen I started my career 36 years ago you would be hard pressed to find a person who had heard of a semiconductor much less knew what one really was. Today, it is still hard to find people who really know semiconductor design and manufacture (especially in the media) even though you can read about it every day, especially now that semiconductors could lead to the next world war.Before you write me off as another click-baiting-chicken-little think about how important semiconductors are to modern life. Not just important, semiconductors are critical to modern life. Not just critical, semiconductors could mean the difference between life and death.Disagree? Imagine our world without electronic devices. Imagine a business or hospital without digital equipment. Imagine a military without high tech gear. Are you getting the picture? Life or death.Now understand that semiconductors are where modern electronics begin and end for that matter. Also understand that the semiconductor chip may have been invented in the United States but today it is a worldwide supply chain.To be clear, no one country can succeed in semiconductor design and manufacture without others. Having grown up in Silicon Valley and spending the majority of my semiconductor professional life traveling the world I know this firsthand, front row seat, I lived it.Being from a military family and a military history enthusiast I also know a little bit about war. My grandfather served in WWI as an Army medic and lived to tell about. In fact, he lived 102 years under my care so I heard all about it. My other Grandfather was at Pearl Harbor, my father served in Korea, and my Uncle in Vietnam. War is hell.One of the strategic things to do when waging a war is to cut off their supply lines, right? Food, water, fuel, raw materials, etc… You can now add semiconductors to that supply list.So why is the United States today cutting off the semiconductor supply line to China? It’s an act of war and if there is an actual war over semiconductors, where will it be fought?Taiwan of course. Taiwan is the semiconductor manufacturing hub of the world. Taiwan is also the Republic of China, which is what my passport says, and even without semiconductors China wants political control over Taiwan. Something like what is happening in Hong Kong only with a full-on war declared.Why is Taiwan so important to the semiconductor supply chain? Because Taiwan is the home of TSMC (Taiwan Semiconductor Corporation), the worldwide champion of semiconductor manufacturing. My first book “Fabless: The Transformation of the Semiconductor Industry” goes into more detail on how TSMC came about but the bottom line is; It’s all about the ecosystem (supply chain). Hundreds of companies around the world brought us to where we are today and nothing short of a war can stop the semiconductor ecosystem from succeeding.Could it even be possible? China at war with the US through Taiwan? Ten years ago from the Lobby of Hotel Royal in Hsinchu I would have said absolutely not. Today, sheltering in Silicon Valley, given the current political instability and oncoming economic challenges, given the eye-for-an-eye +1 behavior of the US and China leadership, I say war is probable. Unless of course the world recognizes semiconductors as a matter of life or death and gets civilized around it. Just my semiconductor professional opinion of course. [post_title] => Will the U.S. and China go to War for TSMC? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => will-the-u-s-and-china-go-to-war-over-tsmc [to_ping] => [pinged] => [post_modified] => 2020-10-04 11:03:58 [post_modified_gmt] => 2020-10-04 18:03:58 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291492 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 22 [filter] => raw [4] => WP_Post Object [ID] => 291429 [post_author] => 28 [post_date] => 2020-10-02 06:00:29 [post_date_gmt] => 2020-10-02 13:00:29 [post_content] => Dean founded IC Manage in 2003, a company that he has helped expand to become the IC/SoC design and IP management technology leader. Dean was also founder, President and CEO of Barracuda Networks from 2003 to 2012, where he built and expanded Barracuda from a spam and virus firewall provider to a broad line enterprise technology company with more than 150,000 customers.Dean was the founder of Boldfish, a leading provider of enterprise messaging solutions that was acquired by Siebel Systems in 2003. Dean was also founder, President and CEO of Design Acceleration, Inc (DAI), a maker of superior design analysis and verification tools. Cadence Design Systems acquired DAI in 1998. Dean was VP of Product Engineering at the 3DO Company and was instrumental in the development of the PowerPC architecture at Apple Computer. Dean received his BSEE from the University of Michigan, Ann Arbor and MSEE from the University of California, Berkeley.We see the recent publication of the Blueprint for EDA Infrastructure white paper  - how has the availability of on demand cloud computing changed the requirements of design management?We are seeing very strong interest in hybrid cloud compute for IC design teams to keep their capital expenditures under control and be more agile in terms of bringing compute resources online quickly. Capacity planning is a hard problem with having to balance budgets, lead times and project schedule pressure. The widespread availability of commodity cloud CPUs provide a lot of promise, but EDA applications require a large amount of storage (tool trees, foundry PDKs, extraction data, etc.) and demand fast, shared storage as well. To get large data sets into the cloud takes days or even weeks and shared storage in the cloud tends to be both expensive and slower than on premise storage.Design management for cloud must streamline the process of getting both repository and generated data to the cloud, minimize the cost of storing it there and use the cheapest, fastest possible storage devices that don’t create bottlenecks for 100s to 1000s of concurrent jobs. This is no small order and we are seeing great results so far with PeerCache for running a wide range of EDA applications in the cloud.What have successful teams done to utilize the cloud to win?Winning means reducing design costs, increasing efficiency of the design team, and getting more product to market faster. It’s not as simple as just picking a cloud vendor and setting up a VPN to run jobs. Costs can quickly spiral out of control in a cloud compute infrastructure and performance issues abound. The successful teams have leadership with a clear plan to leverage the cloud for either all or some of their compute needs.Most of the successful large scale teams utilize their fixed cost, fixed capacity and fixed throughput on-premise compute infrastructure and augment this as needed with additional cloud compute.They need to decide what types of jobs will run in the cloud. They need to establish a dynamic means of routing the jobs as appropriate. They have made the use of the cloud completely seamless for their engineers. Engineers don't even necessarily know if the job is running on premise or in the cloud.Having the data necessary to run a job in the cloud is the challenge. The winners have a central repository of design data and utilize IC Manage Peercache to make the managed design data and the non-managed, tool generated data appear in the cloud instantly for the job to run. They need the jobs to run without modification.I’m happy to say that the investments IC Manage has made in our Global Design Platform, PeerCache and Envision products enable these teams to successfully leverage the cloud for competitive advantage.What issues do globally distributed teams face for their design management and how do you solve them?We’ve seen data management methodologies break down when teams tried to transition from geographically isolated design projects to a center of excellence or IP based design methodology. When the teams work in isolation, managing each project’s data in a local repository is effective, as long as they don’t need to send real-time or even daily updates to remote sites. When shifting to more agile methods to align available engineering expertise to meet project demands on a global scale, this localized methodology fails since it has dozens of repositories with conflicting versions of the same data and no clear genealogy.As we pointed out in the IC Manage Blueprint for EDA Infrastructure white paper, the amount of data required to design, verify and tape out state of the art chips is just too large to manage in bulk. It’s 10s of millions of files, 100’s of terabytes of data that all have to be up to date, correct and consistent. Dealing with that in bulk is just impossible. We use meta data to increase efficiency.Let me explain - using metadata allows us to organize our design components, their interdependencies and current state of completion in a high level configuration or component database. Rather that having to analyze millions of files to extract information, the newest version of our Global Design Platform called GDPXL provides high level web and automation frameworks that can query millions of relevant metadata records in seconds to answer questions like “who last edited the most recently released USB3.0 IP targeted for a specific 20nm technology.What projects have used it so far?”We represent very large devices in the 7nm and 5nm range and create data sets for design, verification, integration and tapeout at any site in a few seconds while maintaining 100% traceability of design changes. This is really a game changer for engineers, managers and executives to get accurate information and collaborate across the globe.To deal with the sheer volume of both design repository data and generated data, our PeerCache product leverages metadata techniques to virtually project datasets to any remote site or into the cloud instantly. A metadata representation of the data that a user needs - again, EDA tools trees, PDK, design source, extracted results - is available in a few seconds and the great thing is that no expensive network storage is needed for that user’s data. This is how we help design teams have jobs up and running in public clouds in a few seconds instead of hours.What issues do teams face in M A and how do you merge design methodology?We’ve certainly seen a large number of our customers in M A scenarios over the past years. The biggest challenges happen when teams with completely different philosophies and methodologies are forced together. A lot of friction can be generated between teams that have invested deeply in automation and scalable data management methodologies as a strategic advantage vs. teams that have considered data management to be an overhead cost and live with inefficient design practices which add costs in terms of manual intervention and poor product quality.The successful M A projects we have seen consolidate onto a single global design management system quickly. They get their engineers working together and sharing IP right away on a single platform. They have clear leadership and a plan from the top. When our customers need it, we bring in a team of experts to assist or even integrate the data from disparate systems onto the IC Manage Global Design Platform. Our customers haveadded 1000’s of engineers to their teams via acquisition and they have migrated them onto the IC Manage platform for maximum productivity and reliability in only a few months.Platform flexibility, scalability, and expertise are key to making this happen so quickly. This is especially true in larger scale acquisitions.How have you built IC manage to address these challenges?I think the key thing to remember about IC Manage is that we were founded by hardware engineers that were both experienced and frustrated by the available tools for design management. Shiv Sikand our EVP of Engineering frequently refers to “People Who Care” as the ones that can drive change and produce great solutions and deliver great support.After 17 years in the Design Management business, we have the industry's most robust track record and strongest reputation for Design Management. We identify the “people who care” and bring them onto the team at IC Manage.We pride ourselves on a level of service that is unparalleled in the industry. Our teams are available 24x7 with senior members to solve any issues our customers encounter in their global infrastructure. We stay ahead of the curve for our customers because they count on us to help them adapt through technology and organizational change. [post_title] => CEO Interview: Dean Drako of IC Manage [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => ceo-interview [to_ping] => [pinged] => [post_modified] => 2020-10-01 13:31:25 [post_modified_gmt] => 2020-10-01 20:31:25 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291429 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [5] => WP_Post Object [ID] => 291416 [post_author] => 13 [post_date] => 2020-10-01 10:00:31 [post_date_gmt] => 2020-10-01 17:00:31 [post_content] => The world of SPICE simulators is one filled with compromises. Typically, it is possible to choose the highest accuracy and pay a performance and capacity penalty, or to choose high speed and capacity but give up accuracy in the process. Many semiconductor companies have been turning to Primarius Technologies to help escape these compromises. Over the last ten years, with a team of industry veterans and support from tier one VCs, they have developed a comprehensive SPICE simulation offering that speeds up full SPICE, offers extremely accurate high-speed SPICE and adds some unique features to enable statistical analysis and Design for Yield (DFY).[caption id="attachment_291439" align="aligncenter" width="632"] SPICE Simulation[/caption]In an upcoming free webinar to air on October 8th at 10AM Pacific time, Yeuh Wang from Primarius will present a complete overview of their NanoSpice, GigaSpice and NanoSpice Pro products. NanoSpice is a pure SPICE simulator that offers parallel processing implemented such that there is excellent linear scaling as cores are added. NanoSpice offers comprehensive model support and has wide foundry acceptance. NanoSpice offers a capacity of over 50 million elements, and more than a 2X speed up over other pure SPICE simulators. It is ready for FinFET designs from 16 down to 7nm.GigaSpice is a high accuracy alternative to FastSPICE simulators which can be difficult to set up properly and suffer from reduced accuracy. In the webinar Yeuh will talk about how with lower supply voltages and higher speeds, it is not always acceptable to only run the top level of large designs with a less accurate FastSPICE. GigaSpice can handle over 10^9 elements and runs faster than FastSPICE. Primarius has eliminated the difficult process of tuning the simulator with FastSPICE options that can often lead to inaccurate results.Fitting in between these two offerings NanoSpice Pro, is a dual engine multicore SPICE that can run large size designs that would normally require FastSPICE. It offers a manifold improvement in runtimes with the accuracy necessary to tackle all aspects of memory design, among other tasks. It can utilize over 32 cores for parallel processing.The icing on the cake is that Primarius also offers unique DFY capabilities within their SPICE simulation tools. These include Fast PVT, Monte Carlo and High Sigma analysis. They also have sophisticated design for reliability features that can help predict aging effects.The webinar will cover a lot of material, including benchmark results and a deeper dive into the technology than we can offer here. If you are looking for a way to improve the speed, accuracy, or usability of your SPICE flows, this webinar will be worth your time. You can register here for the webinar for October 8th at 10AM Pacific time.About PrimariusPrimarius was founded in 2010 by a group of industry veterans, and has seven worldwide offices in Beijing, Hsinchu, Jinan, Seoul, Shanghai, and Silicon Valley. Primarius is well recognized as an essential EDA partner for advanced process technology development and high-end chip designs. It has over 100 worldwide customers including all top foundries and tier-one memory houses, and most other leading semiconductor companies. www.primarius.com [post_title] => Free Webinar on SPICE Simulation [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => free-webinar-on-spice-simulation [to_ping] => [pinged] => [post_modified] => 2020-09-30 16:22:03 [post_modified_gmt] => 2020-09-30 23:22:03 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291416 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [6] => WP_Post Object [ID] => 291249 [post_author] => 16 [post_date] => 2020-10-01 06:00:23 [post_date_gmt] => 2020-10-01 13:00:23 [post_content] => I wasn’t familiar with Veriest, I’m guessing you may not be either. They are a design and verification services company based in the Tel Aviv area (Israel). The CEO, Moshe Zalcberg, was earlier GM for Cadence in Israel. Echoes for me of the early days working with Ajoy Bose in Interra. Veriest have a big emphasis in verification, for example jump-starting formal verification at Valens and teaming with Nuvoton to accelerate tight dynamic verification schedules. A Veriest meetup highlighted another and delightfully free service - sharing verification know-how. They host meetup events for verification knowledge sharing, inviting experts from other companies to speak on an area of their expertise. I attended one of these events in September, in which Jyotika Athavale of Intel spoke on functional safety and Laurent Arditi of Arm spoke on using formal for deadlock detection.Jyotika on soft error-rate modelingJyotika is a PE at Intel based in Chandler. She shared insight into soft error rate modeling from a perspective of neural nets. This is highly topical area; we know about functional safety in “standard” logic in an SoC, but AI accelerators are always treated as black boxes for safety. Which of course isn’t a long-term solution. She quoted an MIT paper in which an approaching large truck could be mis-identified as a bird, potentially leading to a fatal collision. That this is possible shouldn’t be a surprise. We’ve already seen many papers on how pixel-level hacking can completely change image identification. Soft errors can do the same thing. Jyotika’s talk was on modeling that soft error rate.She observed that errors can occur in the image memory and in weights, even in computation. The consequences though, based on their empirical studies, are that fatal errors (crash/hang) are more likely than a silent data corruption (such as the bird versus truck example). Here I gather she is talking about NNs implemented on multicore processors. It would be interesting to know how this might apply to systolic array architectures. She also observed that the training phase is inherently error-tolerant since it is a slow iterative process, though I don’t think the same claim could be made for inference.Laurent on improving deadlock detection, debugLaurent is a Sr. PE at Arm in the Nice area in France, particularly expert in formal verification. His topic was on a refinement to deadlock hunting. This is a popular application for formal modeling where problems may be difficult to find in directed or random simulation. This is one of those formal topics that takes a while to wrap your head around, but I think I’ve got it.First, the standard approach to checking for a deadlock in formal is a liveness assertion – checking that something good eventually happens, here say getting an ack following a req . The problem is that such assertions are based on something called Linear Time Logic (LTL). LTL checks along just one time-path. You may prove there’s no deadlock along that path (it escapes) or perhaps there only appears to be a deadlock along that path. In the second case, maybe you didn’t wait long enough. Or maybe it needed a nudge to get out of a local trap. You can add fairness constraints to fix either problem, but constraints can also introduce bugs. They can also expose real problems, a good thing, but this process is pretty hit and miss. The real problem is that you didn’t check exhaustively along all temporal paths. To do that you need to use Computational Tree Logic (CTL). Not a problem for the core engines but assertion languages such as SVA have no way to represent a CTL assertion.CTL checks generated by Questa formalLaurent used Mentor Questa Formal for verification. Given a standard (LTL) liveness assertion, this will automatically also generate and run a CTL check under the hood. Which bypasses the problem of not being able to write these checks. You get both checks, in Laurent’s terms a maybe-escapable deadlock check (the LTL version) and the definitely not escapable check (the CTL version). Between these you can figure out if you have a problem. Then you can decide if you want to add constraints or pass back to design as a real bug. He makes the point that getting to this conclusion is much easier when you have both LTL and CTL checks.Good insights. To register for future Veriest events, and to access the presentation video and slides of this last event, click here.Also Moshe's opening comments to the event here [post_title] => Veriest Meetup Provides Insights on Safety, Deadlocks [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => veriest-hosts-meetup-on-safety-deadlocks [to_ping] => [pinged] => [post_modified] => 2020-10-04 13:39:48 [post_modified_gmt] => 2020-10-04 20:39:48 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291249 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [7] => WP_Post Object [ID] => 291291 [post_author] => 11830 [post_date] => 2020-09-30 10:00:50 [post_date_gmt] => 2020-09-30 17:00:50 [post_content] => Silicon on insulator (SOI) technology has been around a very long time. I recall five-inch wafers full of SoS (silicon on sapphire) devices while working at the RCA Solid State Technology Center back in the dawn of time. Today, the concept of silicon on insulator is alive and well. Companies like GLOBALFOUNDRIES offer a special process twist, called fully depleted silicon on insulator, or FDSOI. This technology offers FInFET-like performance in a much simpler and more cost-effective process technology to achieve superior energy efficiency.I got a chance to preview an excellent webinar on the topic of FDSOI and some additional techniques called body biasing to further enhance power performance. The webinar is presented by Philippe Flatresse, director of business development and marketing team at Dolphin Design. Philippe has very deep knowledge of the technology presented. While earning his PhD degree in Microelectronics from the Institut National Polytechnique de Grenoble Philippe developed the LETISOI SPICE model dedicated to SOI technologies at CEA LETI. He then joined STMicroelectronics Central R D to deploy SOI digital design activity. After ST, he joined SOITEC as an expert for digital applications to participate in the worldwide promotion of SOI technologies. Philippe has a very strong command of FDSOI and its application.The specific technique Philippe discusses in the webinar is adaptive body-biasing. Case studies are presented for the approach in the GLOBALFOUNDRIES 22FDX technology. Philippe begins with an overview of the ways body biasing has been deployed. Body bias is used to dynamically adjust the threshold voltage (Vt) of a CMOS transistor. The subject of the webinar is adaptive body bias (ABB), which compensates for temperature variations in the low Vdd range and aging variations in the normal to high Vdd range.Philippe discussed the ABB IP design kit, which is a collaboration between Dolphin and GF. He then reviews the various versions of ABB IP that are available and what applications best fit their use. Example results are then presented for a ARM Cortex M4 design on GF22FDX technology. The results presented are quite compelling. The ABB IP portfolio from Dolphin is quite flexible. Several use cases are presented. How to select the appropriate ABB IP driver size is also covered, as is selection and placement of timing monitors and process corners and various sign-off schemes.Detailed, actual silicon results are covered by Philippe. This section includes statistical results with ABB on and off to show the technology’s impact, which is significant. Philippe then summarizes the various approaches covered and their impact. Two comments here caught my eye.Design an energy efficient power management system in weeks instead of monthsDo more with less energyRegarding doing more with less, more includes functionality, performance, battery life, designer productivity, differentiation, market coverage and predictability and SoCs. Less includes constraints, dynamic and leakage power, risks, complexity, re-spins and customer support. There is something for everyone. If you want high power efficiency but don’t want to pay for a FinFET technology, you need to attend this webinar. The webinar will be broadcast on Tuesday, October 6 at 10AM Pacific time. You can register for the webinar here. You can also learn more about Dolphin’s adaptive body bias IP portfolio here.  This technology truly lets you achieve superior energy efficiency. [post_title] => Achieve Superior Energy Efficiency – Body Bias for FDSOI [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => achieve-superior-energy-efficiency-body-bias-for-fdsoi [to_ping] => [pinged] => [post_modified] => 2020-10-01 12:32:48 [post_modified_gmt] => 2020-10-01 19:32:48 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291291 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw [8] => WP_Post Object [ID] => 291266 [post_author] => 19 [post_date] => 2020-09-30 06:00:12 [post_date_gmt] => 2020-09-30 13:00:12 [post_content] => Four years ago, this month, McKinsey published a report - "Monetizing Car Data" - which continues to simultaneously haunt and mock the automotive industry. The report claimed that by 2030 the so-called "car data market" would be worth as much as $750B.SOURCE: McKinseyThis report spawned dozens of internal car data initiatives at car makers and fueled the dreams of startups while draining the pockets of investors. Four years later the industry is still coming to grips with the meaning of the report and its impact - including the realization that a lot of that "value" was derived from prosaic matters such as customer retention and cost avoidance.That being said, the effort to extract value from vehicle data is a noble if somewhat quixotic cause. The proposition was brought home this week when General Motors announced that its Super Cruise semi-autonomous driving function will require a $25/month subscription (or a $15 add-on for an existing OnStar subscriber). If vehicle data is so valuable, why on earth is GM CHARGING customers for the privilege of connectivity?This begs the question as to why ANY car company is charging a subscription beyond anything more nominal than Tesla Motors' $10/month premium connectivity package. Is access to Super Cruise worth more to the customer than an annual subscription to Netflix or Amazon Prime...combined?I was watching a recording of Rupert Mitchell, chief strategy officer for WM Motor Technology Group Company of China, presenting at MOVE America last week in which he noted the importance of vehicle connectivity. Mitchell cites a newer McKinsey study of vehicle owners in China 61% of whom said they would switch brands for better connectivity.SOURCE: McKinsey, WM MotorMitchell illustrated the importance of connectivity by describing how he got rid of the three-year-old Lexus hybrid that he used to drive in Hong Kong because when he was crossing bridges, such as the two-year-old Stonecutter's Bridge in Hong Kong the satnav in his car showed him driving over water.Mitchell's experience reminded me of the I-35 bridge collapse in Minneapolis in 2007, which multiple map providers at the time struggled to account for in their navigation systems. Thirteen years later, the auto industry has yet to solve the bridge out problem largely because map providers and car makers haven't solved the twin connectivity and map updating problem.As the industry shifts - more rapidly than many originally thought - to electrified powertrains and in-dash systems powered by Google, vehicle connectivity will become even more essential. Consumers may be willing to pay something for some portfolio of services, but car makers must be mindful of what is lost where and when customers choose not to pay and prefer to disconnect.Mitchell highlighted, near the end of his talk, his company's use of "data walls" to represent live vehicle data with analytics from the company's connected fleet of vehicles travelling throughout China. The WM Motor data wall (illustrated above) is not unlike similar data walls visible in the headquarters of most auto makers across China.As I have noted in the past, Chinese auto makers produce nearly one third of all automobiles on the planet. (Don't worry, only a tiny fraction of these vehicles are actually exported.) In spite of the enormous number of vehicles China is pouring onto its roads, the companies making those vehicles are increasingly focused on keeping track of every one of those vehicles and monitoring their performance and status. This is especially important for cars with electrified powertrains.When Toyota announced a deal nine years ago with Microsoft Azure to build a connected car eco-system, I imagined Toyota CEO Akio Toyoda overseeing a global connected car command center where Toyota vehicles the world over could be monitored. Needless to say this did not happen and has not happened. In fact, Toyota has shifted its towering and as-yet unrealized cloud car plans to Amazon Web Services.GM, too, has made many proclamations regarding its connected cars, and, yet, GM insists on charging customers for connectivity which has translated into a massive population of GM vehicles with inactive or only partially functioning on-board modems. GM may have a data wall of its own - but many of the cars in its network are not reporting their data.WM Motor is but one in a growing cadre of Chinese car makers that are redefining the car driving and owning experience with connectivity. An idea that was born in the "West" - of connecting cars - has been most aggressively embraced in the "East." Mitchell captures the value proposition most powerfully when he notes near the end of his talk that the data wall provides "a better idea on a real-time basis of the residual value of all of our cars on the road today." What is that worth? $25 a month?? [post_title] => The Car Data Monetization Muddle [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-car-data-monetization-muddle [to_ping] => [pinged] => [post_modified] => 2020-09-30 11:14:17 [post_modified_gmt] => 2020-09-30 18:14:17 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291266 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [9] => WP_Post Object [ID] => 291334 [post_author] => 13 [post_date] => 2020-09-29 10:00:35 [post_date_gmt] => 2020-09-29 17:00:35 [post_content] => Cadence Virtuoso is by far the most popular layout tool for IC design. This is especially true at advanced process nodes. In my opinion one of the key reasons for this is its built-in extension language, SKILL. SKILL is a powerful tool to add time saving and customized functionality to the Virtuoso layout editor. For analog and custom design the command features developed in SKILL can really enhance the layout editing experience.There is a long history and even a precedent for including an extension language in layout editors. Calma’s GDSI and GDSII each had built in languages going back to the late 1970’s. Back then, as is still the case, parts of the vendor’s own product offering were developed in the editor’s extension language. However, customers widely use extension language development to add a competitive edge to their layout environment.In the early days of layout editing software, chip companies themselves developed their own layout editors and other EDA software. As time went on this shifted to the point where chip companies pretty much all now buy commercial software instead of developing it on their own. The same, it seems, is the  case for SKILL code to enhance layout editing features. Many chip companies used internally developed customized SKILL code. However,  as each new process was adopted   it became cost prohibited to both develop and support these layout extensions written in SKILL. Chip companies then began to buy commercial software packages written in SKILL to enhance their flows. This  lead to significant cost savings as these tools  leverages the SKILL commands developed  and tested  in conjunctions with foundries and the top semiconductor customers around the world.  In a nutshell, that is the SkillCAD advantage.SkillCad develops SKILL code to improve layout design efficiency based on their customers’ design requirements. Because they have a single focus, they can produce SKILL code that can make many of the design tasks required in analog, RF and custom design easy and fast for designers. Advanced node design often call for complex structures, such as shielding, twisted lines or matched wires to minimize signal integrity issues. At the same time, there are a myriad of design rules that have to be followed when creating custom layout. SkillCad’s products can create these complex constrained structures rapidly and easily while ensuring they are correct by design.Their Layout Automation Suite (LAS) has over 120 commands that help with the following operations:array manipulation, bus routing, calculation and measurement, connecting metal to devices, density checks, device placement, dummy fill, labels, layer handling, metal path and path segments, metal coloring, multi-part path and guard rings, nets, pins, shape handling, slotted metal, track routing, vias, and viewing.One subset of their commands deals with managing the layout environment to make it easier to use. Setting layer viewing colors and visibility can be tiresome when done manually. SkillCad LAS offers a rich set of commands to control these and other settings.The SkillCad LAS commands for bus routing, array handling and connecting metal to devices speed up what are usually repetitive and slow tasks. Even just turning a bus structure 90 degrees can become a complex error prone operation if done manually. SkillCad offers a comprehensive set of connectivity driven commands for manipulating buses and connecting to instance pins. There are specific features for inductor design. These include via fill operations, guard ring generation, smart shape editing functions, etc. Last but not least, several command groups address requirements for 20nm and below, such as dummy fill and density checks, routing tracks and color-aware routing. In all there are over 120 commands that have been developed over the last 12 years in close consultation with analog, custom and RF design teams at leading chip companies.SkillCad has put together user guides  that shows tutorials and how to use videos for every command in LAS. It is clear from watching it that due to their large customer base and disciplined development that LAS is optimized to offer complex functionality with an easy to use interface. The commands appear to work seamlessly in the Virtuoso environment,   the videos shows the commands going through their paces. More information and the video can be found on the SkillCad website. www.skillcad.com [post_title] => SkillCAD Layout Automation Suite has Over 120 Commands Backed by 60 Customers [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => 291334 [to_ping] => [pinged] => [post_modified] => 2020-09-29 12:06:00 [post_modified_gmt] => 2020-09-29 19:06:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291334 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object [ID] => 291504 [post_author] => 23 [post_date] => 2020-10-04 10:00:41 [post_date_gmt] => 2020-10-04 17:00:41 [post_content] => The first warning sign was “hackproof” in the 360Lock marketing materials. As it turns out, with no surprise to any security professional, the NFC and Bluetooth enabled padlock proved to be anything but secure.Straightforward penetration testing revealed horrible logical and physical security for a padlock that promotes itself as “incorruptible” and “hackproof”!Digital Transformation is a rush to connect our physical world to the global electronic ecosystem to enable better access, integration, and advanced capabilities. Internet of Things (IoT) devices are often at the forefront of this movement, turning normal devices into ‘smart’ devices. Sometimes even the best ideas fail when it comes to design and execution.This padlock has several innovative features such as connectivity to mobile applications, an included RFID wristband and tag for easy unlocking, configurability to add access for others, and a detailed history log. What it lacks however, is actual security.Security theaterSimple pentesting proved what was likely a foregone conclusion. The kickstarter funded lock is neither hackproof nor secure. Testers found that simple replay attacks could trick the logic to open the device. Additionally, crude brute-force methods were able to compromise the integrity of the lock mechanism. Pounding it with a hammer quickly defeated the padlock.The results highlighted that the $40 lock is not robust and better served as a visual deterrent, casual locking device, or novelty item.An industry problemA massive quantity and vast diversity of smart devices are emerging. Most connect to the internet and require a high degree of security. Connectivity accentuates vulnerabilities. Sadly, many of the IoT devices consumers and businesses are embracing lack the necessary measure for security rigor, leaving users exposed and data vulnerable.The 360Lock is not the only device that has poor security, but it does highlight two important points, emphasizing overall industry challenges.First, never trust any product that claims to be ‘unhackable’. Seasoned security professionals would never make such an outlandish assertion as to say a device is hackproof! The fact that 360Lock promoted their product in this way was the only indicator needed to instill great skepticism.Second, this device’s weaknesses highlight the need for proper data transport security. Man-in-the-Middle (MitM) attacks, such as a replay attacks, are common tactics for hackers. Transactional security is absolutely critical to protect data and requests. Unfortunately, securing data in-transit between IoT devices on the edge and phones/PC/cloud-services requires the right expertise and tools. Most failures occur in how data protections are implemented and managed. As a rule, if a product manufacturer is not detailing their security, they likely do not have quality capabilities in place.Painful lessonsConsumers must be wary and realize that even dedicated security products, such as padlocks, can be victimized by poor development decisions. Trendy features are no replacement for solid security and reliability. IoT devices are often much less secure than the marketing materials and salesperson will reveal. Look for reputable manufacturers who have committed to work with the best technology, security integrators, and verification practices. Every consumer and business is responsible for understanding the risks accompanying the benefits of new technology.Interested in more? Follow me on LinkedIn, Medium, and Twitter (@Matt_Rosenquist) to hear insights, rants, and what is going on in cybersecurity. [post_title] => Painful IoT Security Lessons Highlighted by a Digital Padlock [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => painful-iot-security-lessons-highlighted-by-a-digital-padlock [to_ping] => [pinged] => [post_modified] => 2020-10-02 14:15:31 [post_modified_gmt] => 2020-10-02 21:15:31 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291504 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw [comment_count] => 0 [current_comment] => -1 [found_posts] => 7259 [max_num_pages] => 726 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_favicon] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => 443e714a5290f77b0df02e2f78f50560 [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array [0] => query_vars_hash [1] => query_vars_changed [compat_methods:WP_Query:private] => Array [0] => init_query_flags [1] => parse_tax_query [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => [tribe_controller] => Tribe\Events\Views\V2\Query\Event_Query_Controller Object [filtering_query:protected] => WP_Query Object *RECURSION* Uber Technologies won’t be reporting its latest earnings for another month, but when it does so in November the news is not expected to be good. In an effort to flip the script in advance of that report and distract attention from the ongoing COVID-19-induced decline in its core ride hailing business, Uber has launched Uber Green Read More At the recent TSMC OIP Ecosystem Forum and Technology virtual events, TSMC re-affirmed their previous prediction that 5G is going to be a multi-year silicon mega-trend with the biggest drivers being the ramp up of 5G handsets, supporting infrastructure and the continued growth of high performance computing (HPC).We all want Read More The semiconductor industry has never been more exciting than it is today and that is a mouthful given what we have accomplished over the last 50 years. From mainframe computers to a supercomputer in our pockets or on our wrists. Even if you don’t believe in miracles, semiconductor technology comes really close, absolutely.U.S. Read More Dean founded IC Manage in 2003, a company that he has helped expand to become the IC/SoC design and IP management technology leader. Dean was also founder, President and CEO of Barracuda Networks from 2003 to 2012, where he built and expanded Barracuda from a spam and virus firewall provider to a broad line enterprise technology Read More The world of SPICE simulators is one filled with compromises. Typically, it is possible to choose the highest accuracy and pay a performance and capacity penalty, or to choose high speed and capacity but give up accuracy in the process. Many semiconductor companies have been turning to Primarius Technologies to help escape these Read More I wasn’t familiar with Veriest, I’m guessing you may not be either. They are a design and verification services company based in the Tel Aviv area (Israel). The CEO, Moshe Zalcberg, was earlier GM for Cadence in Israel. Echoes for me of the early days working with Ajoy Bose in Interra. Veriest have a big emphasis in verification, for Read More Silicon on insulator (SOI) technology has been around a very long time. I recall five-inch wafers full of SoS (silicon on sapphire) devices while working at the RCA Solid State Technology Center back in the dawn of time. Today, the concept of silicon on insulator is alive and well. Companies like GLOBALFOUNDRIES offer a special Read More Four years ago, this month, McKinsey published a report Monetizing Car Data which continues to simultaneously haunt and mock the automotive industry. The report claimed that by 2030 the so-called car data market would be worth as much as $750B.SOURCE: McKinseyThis report spawned Read More Cadence Virtuoso is by far the most popular layout tool for IC design. This is especially true at advanced process nodes. In my opinion one of the key reasons for this is its built-in extension language, SKILL. SKILL is a powerful tool to add time saving and customized functionality to the Virtuoso layout editor. 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[node_name] => [node_type_id] => Forum [parent_node_id] => 1 [display_order] => 1 [display_in_list] => 1 [lft] => 2 [rgt] => 3 [depth] => 1 [style_id] => 0 [effective_style_id] => 0 [breadcrumb_data] => {"1":{"node_id":1,"title":"Main Category","depth":0,"lft":1,"node_name":null,"node_type_id":"Category"}} [navigation_id] => [effective_navigation_id] => [_relations:protected] => Array [_previousValues:protected] => Array [_options:protected] => Array [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array [_cascadeSave:protected] => Array [_behaviors:protected] => [_previousValues:protected] => Array [_options:protected] => Array [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array [_cascadeSave:protected] => Array [_behaviors:protected] => [_previousValues:protected] => Array [_options:protected] => Array [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array [_cascadeSave:protected] => Array [_behaviors:protected] => [populated:protected] => 1Recent Forum Threads5nm wafer cost very highlatest reply by Fred Chen on October 4, 2020started by Fred Chen on October 1, 2020Equivalent ASIC and FPGA designslatest reply by Karl S on October 4, 2020started by vibeguy on September 30, 2020Recent Article CommentsWill the U.S. and China go to War for TSMC?China and all others should seek and earn trust, as any true relationship whether between countries or just two individuals — Arthur Hanson on October 4, 2020Will the U.S. and China go to War for TSMC?At the moment the only other potential player in the leading edge market is Intel. At the moment, Intel clearly — George Storm on October 4, 2020Will the U.S. and China go to War for TSMC?Thank you for continuing to write about this critical topic. One aspect of evaluating China’s potential Taiwan invasion is considering — Blue Devil on October 4, 2020Will the U.S. and China go to War for TSMC?The article fails to take into account S Korea, Japan, United States and Europe. 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[node_name] => [node_type_id] => Forum [parent_node_id] => 1 [display_order] => 1 [display_in_list] => 1 [lft] => 2 [rgt] => 3 [depth] => 1 [style_id] => 0 [effective_style_id] => 0 [breadcrumb_data] => {"1":{"node_id":1,"title":"Main Category","depth":0,"lft":1,"node_name":null,"node_type_id":"Category"}} [navigation_id] => [effective_navigation_id] => [_relations:protected] => Array [_previousValues:protected] => Array [_options:protected] => Array [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array [_cascadeSave:protected] => Array [_behaviors:protected] => [_previousValues:protected] => Array [_options:protected] => Array [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array [_cascadeSave:protected] => Array [_behaviors:protected] => [_previousValues:protected] => Array [_options:protected] => Array [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array [_cascadeSave:protected] => Array [_behaviors:protected] => [populated:protected] => 1Recent Forum Threads5nm wafer cost very highlatest reply by Fred Chen on October 4, 2020started by Fred Chen on October 1, 2020Equivalent ASIC and FPGA designslatest reply by Karl S on October 4, 2020started by vibeguy on September 30, 2020WP_Widget_Media_Image Instance: 7Array [display_widget_title] => on [attachment_id] => 291180 [url] => https://semiwiki.com/wp-content/uploads/2020/09/Semiwiki-Webinar-Advert-v2_400x400.png [title] => [size] => full [width] => 400 [height] => 400 [caption] => [alt] => Semiwiki Webinar Advert v2 400x400 [link_type] => custom [link_url] => https://register.gotowebinar.com/register/291830586844424972?source=SemiWiki [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => 1 [image_title] => [display_widget_mobile] => [rw_opt] => Array [widget_select] => 1 [pageid_276304] => 1 [pageid_281769] => 1 [pageid_281772] => 1Barn2\Plugin\Better_Recent_Comments\Widget Instance: 2Array [title] => Recent Article Comments [number] => 5 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 [rw_opt_exclude] => Array [pageid_274493] => 1Array [title] => Recent Article Comments [number] => 5 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 [rw_opt_exclude] => Array [pageid_274493] => 1Recent Article CommentsWill the U.S. and China go to War for TSMC?China and all others should seek and earn trust, as any true relationship whether between countries or just two individuals — Arthur Hanson on October 4, 2020Will the U.S. and China go to War for TSMC?At the moment the only other potential player in the leading edge market is Intel. At the moment, Intel clearly — George Storm on October 4, 2020Will the U.S. and China go to War for TSMC?Thank you for continuing to write about this critical topic. One aspect of evaluating China’s potential Taiwan invasion is considering — Blue Devil on October 4, 2020Will the U.S. and China go to War for TSMC?The article fails to take into account S Korea, Japan, United States and Europe. TSMC 'only' command a 50+ percent — phwting on October 4, 2020Will the U.S. and China go to War for TSMC?per Daniel's posting....https://www.reuters.com/article/us-usa-china-smic/u-s-imposes-curbs-on-exports-to-chinas-top-chipmaker-smic-idUSKBN26H0LN — john_lu@morrisonexpress on October 4, 2020WP_Widget_Media_Image Instance: 12Array [display_widget_title] => on [size] => full [width] => 400 [height] => 400 [caption] => [alt] => Aldec PCIe Verification Webinar SemiWiki [link_type] => custom [link_url] => https://bit.ly/2GaJBb9 [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => [attachment_id] => 291496 [url] => https://semiwiki.com/wp-content/uploads/2020/10/Aldec-PCIe-Verification-Webinar-SemiWiki.jpg [title] => [rw_opt] => Array [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 [display_widget_mobile] =>

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