ElecDude

Time 2020-10-05 14:04:38

Web Name: ElecDude

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ElecDude,

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$monitor("@%3t :: foo=%b, a=%x, b=%x, c1=%x, c2=%x, c3=%x, cif1=%x ,cif2=%x ,cif3=%x", $realtime,foo,a,b,c1,c2,c3,cif1,cif2,cif3); #10 foo=1; #5 a=a+1; #10 foo=0; #5 b=b+1; #10 foo=1; endendmodule@ 0 :: foo=x, a=1, b=3, c1=X, c2=X, c3=3, cif1=3 ,cif2=3 ,cif3=3 @ 10 :: foo=1, a=1, b=3, c1=1, c2=1, c3=1, cif1=1 ,cif2=1 ,cif3=1 @ 15 :: foo=1, a=2, b=3, c1=2, c2=2, c3=2, cif1=2 ,cif2=2 ,cif3=2 @ 25 :: foo=0, a=2, b=3, c1=3, c2=3, c3=3, cif1=3 ,cif2=3 ,cif3=3 @ 30 :: foo=0, a=2, b=4, c1=4, c2=4, c3=4, cif1=4 ,cif2=4 ,cif3=4 @ 40 :: foo=1, a=2, b=4, c1=2, c2=2, c3=2, cif1=2 ,cif2=2 ,cif3=2 Based on the simulation, when the condition is X conditional operator outputs X whereas if statement outputs else part. Except this, moreover no difference in execution of these two.Technology has advanced, meanwhile software has become powerful. Xilinx Matlab has worked together to bring hardware cosimulation, where some part of the code will be executing from Xilinx FPGA and input/output can be from Matlab. This is useful for audio, image and signal processing.This video series describes the Hardware/Software cosimulation of verilog and VHDL coding inside FPGA using Xilinx and Matlab. While working in Linux, SED always plays important role in text processing. Here we ve given some common examples of SED usage. Hope it will be a life saving that comes in handy!!!!! Let us know your shortcuts/ commands in comment section below that saved your time...Linux CommandsIn this post, let us see the timescale feature and system tasks that are available in Verilog HDL with brief examples.`timescaledirective specifies the time unit and time precision of the modules that follow it. The time unit is the unit of measurement for time values such as the simulation time and delay values.Syntax:`timescale time_unit / time_precision Thetime_unitargument specifies the unit of measurement for times and delays.Thetime_precisionargument specifies how delay values are rounded before being used in simulation. The smallesttime_precisionargument of all the 'timescale compiler directives in the design determines the precision of the time unit of the simulation.Thetime_precisionargument shall be at least as precise as thetime_unitargument; it cannot specify a longer unit of time thantime_unit. The integers in these arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100. The character strings "s,ms, us, ns,ps, andfs" representunits of measurement;Example:`timescale 1ns/100psHere in the above example,time_unitis 1ns time_precisionis 100ps. So the delay of #1 in the code is equivalent to 1ns delay in simulation. The delay of #1.56 will be rounded to 1.6ns.i.e. the decimal fraction will beroundedto in multiples of thetime_precisionvalue. Each #delay value is rounded to time delays w.r.t the timescale specified and added to the current simulation time.Some of the system tasks on timescale are $printtimescale()prints the timescale settings of the current scope of the file. $timeformat(..,..,,,) system taskThe $timeformatsystem task performs the following two operations:ØIt sets the time unit for all later-entered delays entered interactively.ØIt sets the time unit, precision number, suffix string, and minimum field width for all %t formats specified in all modules that follow in the source description until another $timeformatsystem task is invoked.Syntax for $timeformatis$timeformat(units_number,precision_number,suffix_string,minimum_field_width) ;Example:$timeformat(-9,3,"ns",8);This will display any %t string in ns with 3 digits precision, and 8 characters string size.Let us see the code for the example used for different timescale settings $timeformatsystem task.initialbegin$timeformat(-9,3,"ns",8);#1$display("\n1) %t",$realtime);#10.5$display("\n2) %t",$realtime);#10.56 $display("\n3) %t",$realtime);#10.56 $display("\n4) %t",$realtime);#11.46 $display("\n5) %t",$realtime);$finish;The output of the above code with different timescale values are illustrated in the below table.Similarly you could calculate for different timescale values. If you've any queries, plz do comment it.If you enjoyed this post plz let us know your views via comments.This helps us to do much more better.Thankyou.In this post, let s see how to remove the new line character or line break in a text file and save the result in another text file.Refer to other posts File handling, RegEx.To accomplish the removal of new line character, we use RegEx substitution operator. The code for substitution is as below, $a =~ s/\n//; # $a is the variable in which the replacement takes place The input to the script is through command line arguments. The command line inputs are stored in the array variable @ARGV (please note the CAPS). First we check the size. If no command line arguments is specified, the size of ARGV is -1. If so, the script prints the usage exits, using the in-built function die().unless($#ARGV 0) { $in_file=$ARGV[0];else { die "\nUsage:\n remove_new_line.pl input_file If valid input is provided, then open the specified file in read mode as below. If unable to open the file, exit with a note printed. $! Is the Perl system variable which prints the error from the OS. open FIN, " $in_file" or die "Unable to read '$in_file' :$!"; Create the output file by appending the name new_ to the input file name.open FOUT, " new_$in_file" or die "Unable to create 'new_$in_file' :$!"; Then create a loop, that executes for each line of the input file. Then remove the newline character and write back the result to output file.while ($a= FIN ) { # remove \n character $a =~ s/\n//; # write the new data to text print FOUT $a; Perl offers many easier ways to manipulate string, which is yet powerful with RegEx. In this post, the various functions available in Perl for string manipulation is explained with examples. A regular expression or RegEx is a string of characters that define the pattern or patterns you are viewing. The syntax of regular expressions in Perl is very similar to what you will find within other regular expression, supporting programs, such as sed, grep, and awk. In this post, Perl regex is illustrated with examples. Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. This saves power by adding more logic to a circuit to the clock by disabling clock switching, so that the flip-flops in them do not have to switch states. As a result, the switching power consumption goes to zero, and only leakage currents are incurred. Clock gating logic can be added into a design in a variety of ways:Coded into the RTL code as enable conditions that can be automatically translated into clock gating logic by synthesis tools.Inserted into the design manually by the RTL designers (typically as module level clock gating) by instantiating library specific ICG (Integrated Clock Gating) cells to gate the clocks of specific modules or registers.Semi-automatically inserted into the RTL by automated clock gating tools. These tools either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically also offer sequential clock gating optimisations. Poor clock gating produces glitches in the output clock, making unwanted clock transitions which may lead to timing violations,etc., and increased power consumption. Here is an Verilog example illustrating the RTL code for clock gating its issues. The below code produces simple clock gating mechanism with an 2-input AND gate, with inputs as CLK CLK_EN. But the greatest disadvantage is that it produces glitches in output as in the below waveform.To overcome the glitches, a latching needs to be added to change the enable only when CLK is high/low. By this way, glitches are avoided produces a good clock for the rest of the block.//GOOD clock gating glitch freealways @ (c_en or clk) begin if (!clk) en_out2 = c_en; // build latchendassign clk_out2 = en_out2 clk;SPI means Serial Pheripheral Interface, is a synchronous serial data link operating in full duplex mode.For detailed information of the Verilog code of SPI Master and Slaves modules, proceed to the below links.SPI MASTER SLAVE Verilog Code - SPI Working Modes of Operation - Applications - Advantages Disadvantages SPI Verilog code - Master Slave code with testbenchFor Verilog code of SPI Master and Slaves modules code download discussions, click here. The basics of handling files are simple, just associate a filehandle with an external file and then use a variety of operators and functions within Perl to read and update the data stored within the data stream associated with the filehandle. The filehandle is the name for an I/O connection between the Perl process and the outside world. A filehandle is a named internal Perl structure that associates a physical file with a name. The mode of operation must be specified for the filehandle is opened. Three basic file handles are - STDIN, STDOUT, and STDERR which represent standard input, standard output and standard error devices respectively. Apart from these, any number of filehandles can be added in the code.It is a good practice to use capital letters for filehandles. And for safe operation, it is always recommended to use the DIE(....) function for file open which will terminate the program when it fails to open the file.open(LOG," ",$logfilename) || die "Unable to open the file(log.txt) in append mode!!!";To close a file simply call the CLOSE(...) function with the filehandle as input. All the filehanldes are automatically closed when the Perl program terminates. The syntax isclose(FILEHANDLE);Writing data to a file is simply like printing to STDOUT, except the filehandle is used between the print keyword data.Example:print FH2W "Hello!! This is 1st line...\n";File tests are performed on file handles to determine the file properties. For example e FileHandle returns true if the file pointed by FileHandle exists in the system. The below table shows the different file test that can be performed in Perl. Note that the CAPITAL and small letter tests produces different results.Enter your email address:Delivered by FeedBurnerStay tuned to new posts...IMAGE PROCESSING IN VERILOG - ADD IMAGES IN VERILOG - MATLAB XILINX MODELSIM In previous postings, we have seen how to C onvert an I mage into T ext file for processing in HDL (verilog, VHDL) Now let us see how to ...

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